ASIC Design Engineer – ISP Imaging Pipeline RTL

XPENG; Kuala Lumpur; On-site; MYR 90,000 - 150,000; Full time

Benefits offered by this job

Pension

Bonus potential

Growth with XPENG Europe

Job summary

XPENG is seeking an ISP RTL Design Engineer in Malaysia to develop RTL for ISP pipeline blocks and collaborate with DV, algorithm teams and senior engineers. You will optimize dataflow, line buffers, and PPA considerations while ensuring bit-true alignment with the reference model.

The role requires hands-on Verilog/SystemVerilog with SVA, AMBA familiarity and experience with EDA tools. Knowledge of CFA patterns and camera imaging pipelines is essential.

Qualifications

• BS or above in Microelectronics / EE / Communications / CS or related field.
• 3+ years of digital IC front-end experience, including 1+ year on ISP modules.
• Proficient in Verilog / SystemVerilog; familiar with SVA.
• Hands-on with mainstream EDA tools.
• Familiar with AMBA protocols/ISP Domain
• Solid understanding of the camera imaging pipeline and the role of each stage.
• Familiar with mainstream CFA patterns and their processing differences.
• Able to discuss fixed-point precision, error accumulation and line-buffer trade-offs with algorithm engineers.

Responsibilities

• ISP Module RTL Design: design and implement RTL for blocks in the ISP pipeline.
• Contribute to dataflow, line buffer and caching decisions; support PPA trade-offs across image quality, area, bandwidth and power.
• Work with the algorithm team on fixed-point and hardware-friendly transformations; ensure bit-true alignment between RTL and the reference model.
• Collaborate with DV on the verification plan and sanity testbenches; assist in silicon bring-up, image-quality debug and RTL ECOs.
• Perform code review, Lint, CDC / RDC and basic low-power checks; deliver module-level design documentation.

Skills

Verilog/SystemVerilog

SVA

AMBA protocols

CFA patterns

Fixed-point precision

Camera imaging pipeline

Dataflow & PPA trade-offs

Education

BS or above in Microelectronics / EE / Communications / CS or related field

Tools

Mainstream EDA tools

EDA Tool familiarity

Job description

XPENG is seeking an ISP RTL Design Engineer in Malaysia to develop RTL for ISP pipeline blocks and collaborate with DV, algorithm teams and senior engineers. You will optimize dataflow, line buffers, and PPA considerations while ensuring bit-true alignment with the reference model.

The role requires hands-on Verilog/SystemVerilog with SVA, AMBA familiarity and experience with EDA tools. Knowledge of CFA patterns and camera imaging pipelines is essential.