Senior Design Verification Engineer (FPGA/Emulation)

UST; Penang; On-site; MYR 96,000 - 168,000; Full time

Job summary

UST in Malaysia is seeking a Design Verification Engineer to develop and execute verification plans for SoC/IP designs, perform simulation and debugging, and support Emulation/FPGA-based verification. You will write and debug C/C++ test code and collaborate closely with RTL/design teams to resolve issues.

The role requires 4+ years in design verification, strong SystemVerilog/UVM, and hands-on Emulation/FPGA experience, with a degree in Electrical/Electronic or Computer Engineering and solid

Qualifications

• 4+ years of experience in Design Verification.
• Bachelor’s/Master’s degree in Electrical/Electronic Engineering, Computer Engineering, or related field
• Strong experience in SystemVerilog/UVM and DV methodologies.
• Hands-on experience with Emulation or FPGA is preferred.
• Proficiency in C/C++ programming.
• Experience with SoC/IP verification, debugging, and simulation tools.

Responsibilities

• Develop and execute verification plans for SoC/IP designs.
• Perform simulation, debugging, and functional verification.
• Support Emulation/FPGA-based verification.
• Write and debug C/C++ test code.
• Work closely with RTL/design teams to identify and resolve issues.

Skills

C/C++ programming

Design verification

DV methodologies

SystemVerilog/UVM

Education

Bachelor’s/Master’s degree in Electrical/Electronic Engineering, Computer Engineering, or related field

Tools

Emulation

FPGA

Simulation tools

Job description

Responsibilities

• Develop and execute verification plans for SoC/IP designs.
• Perform simulation, debugging, and functional verification.
• Support Emulation/FPGA-based verification.
• Write and debug C/C++ test code.
• Work closely with RTL/design teams to identify and resolve issues.

Requirements

• 4+ years of experience in Design Verification.
• Bachelor’s/Master’s degree in Electrical/Electronic Engineering, Computer Engineering, or related field.
• Strong experience in SystemVerilog/UVM and DV methodologies.
• Hands-on experience with Emulation or FPGA is preferred.
• Proficiency in C/C++ programming.
• Experience with SoC/IP verification, debugging, and simulation tools.