SoC DFX SMS Engineer

Infinecs Systems Pvt. Ltd.; Malaysia; On-site; MYR 120,000 - 180,000; Full time

Job summary

Infinecs Systems Pvt. Ltd. is seeking an experienced engineer to focus on SoC DFX SMS design, verification, and post-silicon ATE pattern debugging within the design flow. Responsibilities include memory components such as SRAM/ROM; development of BIST, memory repair tests, and production test optimization.

The candidate should have MBIST/DFT, SoC verification, and RTL quality check experience, with strong scripting skills in Perl, Tcl, or Python, and good English/Mandarin communication.

Qualifications

• MBIST, DFX/DFT, SoC verification, memory test experience.
• Process, device or ASIC design background.
• Knowledge in two or more fields: SCAN, MBIST, RTL design, STA, Verification, and Emulation.
• Strong programming in Perl, Tcl or Python.

Responsibilities

• Implement SoC DFX SMS design on SRAM, ROM, Latch Arrays, etc.
• Develop and verify tile level and chip level bist and memory repair test cases.
• Develop high coverage and cost-effective test patterns for production test.
• Support DFX SMS design quality check and documentation tasks.
• Support DFX silicon bring up and ATE test.

Skills

MBIST

DFX/DFT

SoC verification

Memory test

RTL design

STA

Emulation

Synthesis

LEC

CDC

Perl

Python

Tcl

English Mandarin

Education

Master's degree

Bachelor's degree

Tools

Perl scripting

Python scripting

Tcl scripting

Job description

This role is focused on SoC DFX SMS design, verification, and post-silicon ATE pattern debugging within the SoC design flow. The engineer will be responsible for implementing and validating DFX SMS solutions for memory components such as SRAM, ROM, and latch arrays, while supporting memory repair test development and production test optimization. The ideal candidate is a collaborative team player with strong MBIST design and verification experience, capable of providing technical support across Front-End Design, Physical Design, SoC Design Verification, and other DFX teams. Knowledge of STA, verification methodologies, and RTL quality checks would be an added advantage.

Responsibilities include (but are not limited to):

• Implement SoC DFX SMS design on SRAM, ROM, Latch Arrays, etc.
• Develop and verify tile level and chip level bist and memory repair test cases.
• Develop and verify high coverage and cost-effective test patterns for production test.
• Support DFX SMS design quality check and documentation tasks.
• Support DFX silicon bring up and ATE test.

Requirements:

• Master's degree with 1 year or Bachelor with 3 years' experience at least.
• Minimum 5 years of experience in MBIST, DFX/DFT, SoC verification, memory test, or related semiconductor design activities.
• Solid background on process, device or ASIC design.
• Proven knowledge and expertise on two or more fields of SCAN, MBIST, RTL design, STA, Verification and Emulation.
• Experience in Synthesis, formal/LEC, or CDC will be a plus.
• Prior SoC project test experience is a plus.
• Strong programming and scripting skills in Perl, Tcl or Python will be a strong plus.
• Good verbal, written and communication skill in English and Mandarin.
• Good teamwork spirit and self-driven.