DFT Test Engineer: Boundary Scan & ICT Debug

Celestica; Penang; On-site; MYR 120,000 - 160,000; Full time

Job summary

Celestica is seeking an experienced test engineer focused on design-for-test (DFT) reviews and boundary-scan validation at our Bayan Lepas, Penang site. The role supports early build debug and ensures test points and ICT tooling meet MTRS rules before layout freeze.

The candidate will work closely with design and software teams to drive coverage, resolve testability gaps, and propose DFT rule changes from found escapes or fixture rework. This is a hands-on, manufacturing-floor role.

Qualifications

• Four to eight years in DFT or test engineering.
• Boundary scan, ICT and coverage analysis tooling expected.
• Degree in electrical or electronic engineering.

Responsibilities

• Review schematic and layout against the DFT rule set before freeze, and raise findings with the evidence behind the rule.
• Model structural and functional coverage and report the gap against the MTRS.
• Work the disposition with design and software: test point addition, chain correction or an agreed alternative.
• Verify achieved coverage on the first fixture and record the difference against the claim.
• Support functional test definition and early build debug with the TRL and the on-site test SMEs.
• Propose DFT rule changes from escapes and from fixture rework.

Skills

DFT experience

Boundary scan

ICT tooling

Education

Bachelor's degree in electrical/electronic engineering

Tools

Test instrumentation tools

Job description

Celestica is seeking an experienced test engineer focused on design-for-test (DFT) reviews and boundary-scan validation at our Bayan Lepas, Penang site. The role supports early build debug and ensures test points and ICT tooling meet MTRS rules before layout freeze.

The candidate will work closely with design and software teams to drive coverage, resolve testability gaps, and propose DFT rule changes from found escapes or fixture rework. This is a hands-on, manufacturing-floor role.