DFT Engineer

Pride Global; Penang; On-site; MYR 120,000 - 180,000; Full time

Job summary

Pride Global is seeking an experienced Design-for-Test (DFT) Engineer to deliver high-manufacturing test coverage and optimized test cost for ASICs/SoCs. The role emphasizes robust DFT architectures, scan chains, and modern ATPG techniques.

You will work onsite in Malaysia, collaborating with product engineering to validate DFT implementations and assist silicon bring-up, yield improvement, and test optimization. A strong scripting skillset is required for flow automation.

Qualifications

• Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related discipline.
• 4-15 years of hands-on experience in ASIC/SoC DFT implementation.
• Strong knowledge of Verilog/SystemVerilog/VHDL, digital design, and synthesis.
• Hands-on experience with Synopsys (Design Compiler, DFTMAX, TetraMAX, Fusion Compiler), Siemens Tessent/FastScan/TestKompress, or Cadence Modus/Genus.
• Proficiency in Tcl, Python, or Perl scripting for automation.
• Experience with production DFT flows, ATPG, scan insertion, MBIST/LBIST, and silicon debug is highly preferred.

Responsibilities

• Define and implement chip-level DFT architecture, including scan, MBIST, LBIST, JTAG, IJTAG, and IEEE 1500 wrapper chains.
• Develop test strategies, clock/reset architectures, and DFT specifications for complex SoCs.
• Integrate scan compression solutions using industry-standard EDA tools (Synopsys DFTMAX, Siemens Tessent, Cadence Modus).
• Generate and optimize ATPG patterns for Stuck-at, Transition Delay, Cell-Aware, and Path Delay fault models.
• Verify DFT implementation through RTL and gate-level simulations, and perform pre- and post-layout DFT validation.
• Support silicon bring-up, ATE debugging, failure analysis, and yield improvement in collaboration with product engineering teams.
• Develop automation scripts using Tcl, Python, or Perl to improve DFT flow efficiency.

Skills

Verilog/SV/VHDL

Digital design

Synthesis

Scripting (Tcl/Python/Perl)

Education

Bachelor's or Master's in Electrical/Computer Engineering

Tools

Synopsys Design Compiler

Synopsys DFTMAX

Synopsys TetraMAX

Fusion Compiler

Siemens Tessent/FastScan/TestKompress

Cadence Modus/Genus

Job description

Employment type : Open to Perm & Contract

Working arrangement : Onsite

Salary Range : 15 - 20% Increments

Position Overview

We are seeking an experienced Design-for-Test (DFT) Engineer to develop and implement DFT solutions for high-performance ASICs and SoCs. The role focuses on delivering high manufacturing test coverage, optimized test cost, and efficient test execution while maintaining power, performance, and area (PPA) targets.

Key Responsibilities

• Define and implement chip-level DFT architecture, including scan, MBIST, LBIST, JTAG, IJTAG, and IEEE 1500 wrapper chains.
• Develop test strategies, clock/reset architectures, and DFT specifications for complex SoCs.
• Integrate scan compression solutions using industry-standard EDA tools (Synopsys DFTMAX, Siemens Tessent, Cadence Modus).
• Generate and optimize ATPG patterns for Stuck-at, Transition Delay, Cell-Aware, and Path Delay fault models.
• Verify DFT implementation through RTL and gate-level simulations, and perform pre- and post-layout DFT validation.
• Support silicon bring-up, ATE debugging, failure analysis, and yield improvement in collaboration with product engineering teams.
• Develop automation scripts using Tcl, Python, or Perl to improve DFT flow efficiency.

Requirements

• Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related discipline.
• 4-15 years of hands-on experience in ASIC/SoC DFT implementation.
• Strong knowledge of Verilog/SystemVerilog/VHDL, digital design, and synthesis.
• Hands-on experience with Synopsys (Design Compiler, DFTMAX, TetraMAX, Fusion Compiler), Siemens Tessent/FastScan/TestKompress, or Cadence Modus/Genus.
• Proficiency in Tcl, Python, or Perl scripting for automation.
• Experience with production DFT flows, ATPG, scan insertion, MBIST/LBIST, and silicon debug is highly preferred.