DFX/DFT Engineer

Thundersoft; George Town; On-site; MYR 100,000 - 145,000; Full time

Job summary

Thundersoft is seeking a DFT/ DFx Verification Engineer to verify architecture, design, and implementation of critical DFT and DFD features. You will work with global design teams on test development, tool integration, and ongoing process improvements.

The role emphasizes robust debugging, automation, and collaboration across RTL, firmware, and test environments. The ideal candidate has 3–5 years in DFT verification, strong SystemVerilog/UVM experience, and hands-on scripting skills.

Qualifications

• Bachelor's or Master's degree in Electrical/Electronics/Computer Engineering or related field.
• 3–5 years of DFT Design Verification with strong debugging abilities.
• Experience with SystemVerilog/UVM testbenches for SoCs, including GLS & SDF verifications.
• Hands-on with DFT/DFX methods: Scan, ATPG, MBIST, Boundary Scan, or equivalents.
• Advanced scripting for automation and testbench infra (Tcl, Python, Perl).
• Strong knowledge of digital RTL design and verification flows.

Responsibilities

• Collaborate with architects and firmware engineers to verify new DFT features.
• Estimate effort to write feature tests and adjust test environment.
• Build directed and random DFT verification tests.
• Debug test failures; coordinate with RTL/DFT to fix defects.
• Enhance legacy DFT test plans for new feature development.
• Reproduce post-silicon issues in pre-silicon environment.
• Conduct silicon debug and root-cause analysis with minimal logs.
• Use JTAG protocols for debugging and validation.

Skills

DFT/DFX verification

SystemVerilog/UVM

Debug without logs

Scripting (Tcl, Python, Perl)

RTL design & verification

CG/BA or debugging methodologies

Education

Bachelor's or Master's in Electrical/Electronics/Computer Engineering

Tools

Simulation tools

Emulation tools

GLS & SDF verification

Job description

We are looking for a DFT/ DFx Verification Engineer, you will be primarily responsible for verification of architecture, design, and implementation of critical Design-for-Test (DFT) and Design-for-Debug (DFD) features for cutting edge client's products and will be working with a team of design engineers from various global design locations on design-for-test (DFT) design and implementation, tool and methodology development, project execution and continuous improvement initiatives, this role provides an excellent growth opportunity for robust individuals looking to make a difference.

KEY RESPONSIBLITIES

• Collaborate with architects, design engineers, and firmware engineers to understand the new DFT features to be verified.
• Estimate the time required to write the new feature tests and any required changes to the test environment.
• Build the directed and random DFT verification tests.
• Debug test failures to determine the root cause; work with RTL/DFT and firmware engineers to resolve design defects and correct any test issues.
• Analyze and enhance legacy DFT test plans to accommodate new Design for Debug feature developments.
• Recreate post-silicon failures in pre-silicon environment.
• Conduct silicon debug and root cause analysis with minimal logging support.
• Utilize JTAG protocols for debugging and validation.3

PREFERRED EXPERIENCE

• Bachelor's or Master's degree in Electrical/Electronics/Computer Engineering, or a related field.
• 3 - 5 years of experience in DFT Design Verification with strong debug capabilities.
• Experienced with SystemVerilog/UVM testbench development for complex SoCs Including GLS & SDF verifications.
• Hands-on experience with DFT/DFX methodologies, including Scan, ATPG, MBIST, Boundary Scan, or related techniques.
• Advanced scripting skills (Tcl, Python, Perl, etc.) for automation and testbench infrastructure.
• Deep knowledge of digital design, RTL design, and verification flows.
• Strong troubleshooting and analytical debugging skills with ability to debug without logs.
• Ability to quickly adapt to complex infrastructure environments.
• Excellent hands-on debug skills and attention to detail.
• Proficient in debugging firmware and RTL code using simulation tools.
• Emulation execution background is a plus.