DFT/DFX Engineer

Thundersoft; George Town; On-site; MYR 90,000 - 130,000; Full time

Job summary

Thundersoft is seeking an experienced DFT Verification Engineer in Penang to collaborate with architects and engineers on new DFT features. You will write tests, debug, and optimize test plans while using SystemVerilog/UVM and scripting skills to automate workflows.

The role requires 3–5 years in DFT design verification, strong debugging capabilities, and hands-on experience with emulation and pre/post-silicon validation. Penang-based, on-site position.

Qualifications

• Bachelor's or Master's degree in Electrical/Electronics/Computer Engineering or related field.
• 3-5 years of experience in DFT Design Verification with strong debugging capabilities.
• Experience with SystemVerilog/UVM testbench development for complex SoCs including GLS & SDF verifications.
• Hands-on experience with DFT/DFX methodologies: Scan, ATPG, MBIST, Boundary Scan.
• Advanced scripting skills (Tcl, Python, Perl) for automation and testbench infrastructure.
• Deep knowledge of digital design, RTL design, and verification flows.
• Strong troubleshooting and analytical debugging skills with ability to debug without logs.
• Ability to adapt quickly to complex infrastructure environments.
• Excellent hands-on debugging and attention to detail.
• Proficient in debugging firmware and RTL code using simulation tools.
• Emulation execution background is a plus.

Responsibilities

• Collaborate with architects, design engineers, and firmware engineers to understand new DFT features to be verified.
• Estimate time required to write new feature tests and any needed test-environment changes.
• Build directed and random DFT verification tests.
• Debug test failures to determine root cause; work with RTL/DFT and firmware engineers to resolve design defects and test issues.
• Analyze and enhance legacy DFT test plans for new Design for Debug feature developments.
• Recreate post-silicon failures in pre-silicon environment.
• Conduct silicon debug and root cause analysis with minimal logging support.
• Utilize JTAG protocols for debugging and validation.

Skills

DFT design verification

SystemVerilog/UVM

debugging

RTL design

verification flows

debug without logs

emulation

scripting (Tcl, Python, Perl)

Education

Bachelor's or Master's in Electrical/Electronics/Computer Engineering

Tools

SystemVerilog/UVM

Scripting languages (Tcl, Python, Perl)

Simulation tools

Job description

• Collaborate with architects, design engineers, and firmware engineers to understand the new DFT features to be verified.
• Estimate the time required to write the new feature tests and any required changes to the test environment.
• Build the directed and random DFT verification tests.
• Debug test failures to determine the root cause; work with RTL/DFT and firmware engineers to resolve design defects and correct any test issues.
• Analyze and enhance legacy DFT test plans to accommodate new Design for Debug feature developments.
• Recreate post-silicon failures in pre-silicon environment.
• Conduct silicon debug and root cause analysis with minimal logging support.
• Utilize JTAG protocols for debugging and validation.

PREFERRED EXPERIENCE

• Bachelor's or Master's degree in Electrical/Electronics/Computer Engineering, or a related field.
• 3 - 5 years of experience in DFT Design Verification with strong debug capabilities.
• Experienced with SystemVerilog/UVM testbench development for complex SoCs Including GLS & SDF verifications.
• Hands-on experience with DFT/DFX methodologies, including Scan, ATPG, MBIST, Boundary Scan, or related techniques.
• Advanced scripting skills (Tcl, Python, Perl, etc.) for automation and testbench infrastructure.
• Deep knowledge of digital design, RTL design, and verification flows.
• Strong troubleshooting and analytical debugging skills with ability to debug without logs.
• Ability to quickly adapt to complex infrastructure environments.
• Excellent hands-on debug skills and attention to detail.
• Proficient in debugging firmware and RTL code using simulation tools.
• Emulation execution background is a plus.