DFT Engineer

XINPAL (MALAYSIA) SDN. BHD.; Bayan Lepas; In loco; MYR 60.000 - 90.000; Tempo pieno

Descrizione del lavoro

XinPal Malaysia, part of an MNC based in Singapore, seeks a DFT Engineer in Bayan Lepas, Penang. You will develop test strategies for advanced SoC and AI-SoC designs, focusing on scan-based DFT architectures and testability features.

You will collaborate with design, product engineering and operations teams to optimize test coverage, time and cost across block, chip and system levels, and to support ATE bring-up and failure analysis.

Competenze

• Bachelor's or Master's Degree in Electrical or Computer Engineering.
• 2–4 years of experience in DFT or test development for complex SoCs.
• Knowledge of scan, ATPG, MBIST, LBIST, and boundary scan.
• Experience with die-level screening and multi-stage test insertion.
• Familiarity with ATE environments and yield analysis.

Mansioni

• Define DFT architecture and implement test strategies for complex SoCs and AI-SoCs.
• Develop and execute test patterns for logic, memory, and high-speed interconnects.
• Collaborate with design, product engineering and operations teams to embed testability early in design.
• Drive planning for scan, MBIST, LBIST, boundary scan, and interconnect test flows.
• Analyze coverage, test time and cost trade-offs; support ATE bring-up and failure analysis.

Conoscenze

DFT engineering

Test strategy

ATPG

MBIST

LBIST

Boundary scan

Formazione

Electrical/Computer Engineering degree

Strumenti

ATE systems

Testing equipment

Yield tracking tools

Descrizione del lavoro

XinPal Malaysia is part of an MNC headquartered in Singapore, specializing in delivering innovative technology solutions and supporting cutting-edge semiconductor projects. We are committed to building a high-performing team through innovation, collaboration, and continuous growth opportunities.

We are looking for a DFT Engineer in Bayan Lepas, Penang to support the development and implementation of test strategies for advanced SoC and AI-SoC designs. The role involves DFT architecture, test pattern development, test insertion, coverage analysis, and collaboration with design, product engineering, and operations teams to ensure robust and efficient semiconductor testing.

Implement DFT and test architecture for complex SoCs and advanced products across block-level, chip-level, and final test stages.

Develop and execute test patterns for logic, memory, and high-speed interconnects under the direction of senior leads.

Work with design, product engineering, and operations teams to integrate testability features early in the design cycle.

Drive implementation planning for scan, MBIST, LBIST, boundary scan, and basic interconnect test flows.

Analyze coverage, test time, and test cost trade-offs to support efficient production test execution.

Support ATE bring-up, known-good-die or die-level screening methodologies, and initial failure diagnosis.

Bachelor's or Master's Degree in Electrical Engineering, Computer Engineering or a related field.

2-4 years of experience in DFT, product test, or test development for complex SoCs or advanced packages.

Good working knowledge of scan, ATPG, MBIST, LBIST, and boundary scan methodologies.

Exposure to modern test challenges, including multi-stage test insertion and die-level screening strategies.

Familiarity with ATE environments, yield tracking, and basic failure analysis.