Senior DFT Architect — FPGA/SoC Innovation Leader

Altera; George Town; On-site; MYR 300,000 - 460,000; Full time

Job summary

Altera is seeking a DFT Architect to define, drive, and govern next‑generation DFT architecture across FPGA, SoC, and multi‑die silicon platforms. You will own the end‑to‑end DFT strategy and partner with architecture, RTL, PD, validation, and manufacturing teams to ensure world‑class testability and silicon quality.

You will lead scalable DFT methodologies, drive state‑of‑the‑art architectures for scan, compression, MBIST/LBIST, boundary scan, and in‑system test, while steering multi‑die and

Qualifications

• 15+ years of industry experience with DFT architecture leadership.
• 10+ years architecting and implementing DFT for complex SoC/FPGA/ASIC designs.
• 10+ years in scan architecture, ATPG, compression, MBIST, LBIST, and hierarchical DFT.
• 10+ years RTL-to-GDS DFT integration including scan insertion and STA constraints.
• Experience with IEEE IJTAG/JTAG standards and advanced fault models is a plus.

Responsibilities

• DFT Strategy Ownership — Define and drive long-term DFT architecture for multi-die products.
• Methodology Leadership — Develop scalable DFT flows across RTL, gate-level, and multi-die environments.
• Advanced DFT Architecture — Architect scan, compression, ATPG, MBIST/LBIST, and boundary scan solutions.
• Multi-Die & Packaging DFT — Drive planning for 2.5D/3D ICs, chiplets, and heterogeneous systems.
• Cross-Functional Integration — Collaborate with architecture, RTL, PD, validation, and manufacturing.
• DFT Governance — Establish guidelines, test specs, timing constraints, and signoff criteria.
• Silicon Debug Leadership — Lead root-cause analysis for pre- and post-silicon issues.
• Manufacturing Test Optimization — Improve coverage, test time, yield, and power-aware testing.
• Technology Innovation — Adopt new DFT technologies and automation; mentor engineers.

Skills

DFT architecture

ATPG

MBIST/LBIST

RTL-to-GDS DFT

Boundary scan

2.5D/3D DFT

Scripting (Python)

Cross-functional leadership

Education

Bachelor’s degree in Electrical Engineering or related field

Master’s degree preferred

Tools

Synthesis tools

ATPG tools

Debug/Simulation tools

Formal verification tools

Job description

Altera is seeking a DFT Architect to define, drive, and govern next‑generation DFT architecture across FPGA, SoC, and multi‑die silicon platforms. You will own the end‑to‑end DFT strategy and partner with architecture, RTL, PD, validation, and manufacturing teams to ensure world‑class testability and silicon quality.

You will lead scalable DFT methodologies, drive state‑of‑the‑art architectures for scan, compression, MBIST/LBIST, boundary scan, and in‑system test, while steering multi‑die and