CAD Flow Engineer

UST Malaysia; Bayan Lepas; On-site; MYR 120,000 - 240,000; Full time

Job summary

UST Malaysia is seeking a CAD Flow Engineer to develop and optimize Physical Design implementation flows for advanced-node ASIC/SoC projects in Penang. You will collaborate with multiple design teams to deliver scalable methodologies that boost QoR and turnaround time.

Responsibilities include automating flows using TCL, Python, Perl and Shell scripts, integrating Fusion Compiler, PrimeTime, ICC2, and Formality, and building robust QoR tracking and signoff processes for 5nm/3nm roadmaps.

Qualifications

• 5-8 years of experience in VLSI CAD, Physical Design, Implementation Methodology or Design Automation.
• Strong understanding of digital ASIC implementation flows from RTL to GDSII.
• Hands-on with TCL, Python, Shell scripting.

Responsibilities

• Develop, maintain, and support Physical Design implementation flows across advanced process nodes.
• Customize and optimize flows using Synopsys Fusion Compiler, PrimeTime, ICC2, Formality, and related EDA tools.
• Design and maintain automation frameworks using TCL, Python, Perl, and Shell scripting.
• Create reusable infrastructure for synthesis, floorplanning, placement, CTS, routing, timing closure, and signoff activities.
• Develop QoR tracking, regression, reporting, and design health monitoring solutions.
• Debug flow issues, tool crashes, runtime bottlenecks, and methodology-related challenges.
• Collaborate with implementation teams to improve timing, power, area, congestion, and turnaround time.
• Enable new tool releases and drive tool qualification across projects.
• Develop methodologies for MCMM timing analysis, ECO flows, and signoff convergence.
• Work closely with EDA vendors to investigate tool issues and evaluate new features.
• Support deployment of advanced-node implementation methodologies (5nm, 3nm, and beyond).
• Create and maintain user documentation, flow guidelines, and training materials.

Skills

VLSI CAD

ASIC design

Scripting TCL

Python scripting

Shell scripting

Digital ASIC flows

Education

Bachelor's or Master's in Electronics/Electrical/Computer Engineering

Tools

Synopsys Fusion Compiler

Synopsys PrimeTime

ICC2

Formality

Design Compiler

Job description

Job Overview

We are seeking a highly motivated CAD Flow Engineer to develop, maintain, and enhance Physical Design implementation flows for advanced-node ASIC and SoC projects. The ideal candidate will have strong expertise in EDA tools, automation, methodology development, and flow optimization across RTL-to-GDSII implementation.

The role involves close collaboration with Physical Design, STA, DFT, RTL, and CAD teams to deliver robust, scalable, and efficient design methodologies that improve design productivity, QoR, and turnaround time.

Key Responsibilities

• Develop, maintain, and support Physical Design implementation flows across advanced process nodes.
• Customize and optimize flows using Synopsys Fusion Compiler, PrimeTime, ICC2, Formality, and related EDA tools.
• Design and maintain automation frameworks using TCL, Python, Perl, and Shell scripting.
• Create reusable infrastructure for synthesis, floorplanning, placement, CTS, routing, timing closure, and signoff activities.
• Develop QoR tracking, regression, reporting, and design health monitoring solutions.
• Debug flow issues, tool crashes, runtime bottlenecks, and methodology-related challenges.
• Collaborate with implementation teams to improve timing, power, area, congestion, and turnaround time.
• Enable new tool releases and drive tool qualification across projects.
• Develop methodologies for MCMM timing analysis, ECO flows, and signoff convergence.
• Work closely with EDA vendors to investigate tool issues and evaluate new features.
• Support deployment of advanced-node implementation methodologies (5nm, 3nm, and beyond).
• Create and maintain user documentation, flow guidelines, and training materials.

Required Qualifications

• Bachelor's or Master's degree in Electronics Engineering, Electrical Engineering, Computer Engineering, or related discipline.
• 5-8 years of experience in VLSI CAD, Physical Design, Implementation Methodology, or Design Automation.
• Strong understanding of digital ASIC implementation flows from RTL to GDSII.
• Hands-on experience with:
• Synopsys Fusion Compiler
• Synopsys PrimeTime
• ICC2
• Formality
• Design Compiler
• Strong scripting expertise in:
• TCL (mandatory)
• Python
• Shell scripting
• Experience developing CAD infrastructure, regressions, automation utilities, and flow enhancements.
• Good understanding of:
• Synthesis
• Floorplanning
• Placement
• CTS
• Routing
• Timing Closure
• MCMM Analysis
• Physical Verification
• Experience debugging timing, constraint, and methodology-related issues.
• Familiarity with Linux/Unix environments.