Lead Digital IP Engineer for Next-Gen SoC & RTL

Xinpal

George Town

On-site

MYR 90,000 - 150,000

Full time

30 hours ago
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Job summary

Xinpal in Penang, Malaysia is seeking an experienced Digital Design Engineer to drive end-to-end IP development for next-generation SoC products. The role involves architecture, RTL implementation, and collaboration with DV and Physical Design teams to meet PPA targets.

You will define micro-architectures, develop specifications, and deliver high-quality RTL, timing constraints, and low-power designs. Mandarin proficiency is preferred to liaise with internal stakeholders.

Qualifications

  • Master's or Bachelor's degree in Electrical & Electronics Engineering or related field.
  • Minimum 2 years hands-on experience in Digital IC/RTL Design.
  • Proven experience delivering digital IP from specification through verified RTL.
  • Preferred: CPU architecture, cache coherency, AMBA AXI/CHI/ACE protocols.
  • Experience in high-speed interface/protocol design (DDR, PCIe, USB, UCIe, or CXL).
  • Mandarin proficiency is preferred to liaise with internal stakeholders.

Responsibilities

  • Lead digital IP/module development from concept to SoC integration.
  • Define hardware micro-architecture and develop functional specs.
  • Develop RTL, SDC timing constraints, and low-power designs using UPF.
  • Collaborate with Architecture, DV, and Physical Design teams to meet PPA/timing targets.

Skills

Digital IC/RTL Design
CPU architecture & AMBA protocols
High-speed digital design
Pre-silicon simulation

Education

Master's degree in Electrical & Electronics Engineering
Bachelor's degree in Electrical & Electronics Engineering

Job description

Xinpal in Penang, Malaysia is seeking an experienced Digital Design Engineer to drive end-to-end IP development for next-generation SoC products. The role involves architecture, RTL implementation, and collaboration with DV and Physical Design teams to meet PPA targets.

You will define micro-architectures, develop specifications, and deliver high-quality RTL, timing constraints, and low-power designs. Mandarin proficiency is preferred to liaise with internal stakeholders.

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