Lead SoC IP Digital Design Engineer (RTL/UPF)

XINPAL (MALAYSIA) SDN. BHD.; Bayan Lepas; On-site; MYR 90,000 - 130,000; Full time

Job summary

XinPal Malaysia seeks a Digital Design Engineer (SoC/IP) in Bayan Lepas, Penang to drive hardware IP development from concept to RTL and final SoC integration. You will collaborate with Architecture, Physical Design, and DV to hit PPA targets and timing constraints.

The role requires a minimum of 2 years' experience in Digital IC/RTL Design and hands-on RTL coding with a strong background in CPU architectures, AMBA protocols, and high-speed interfaces.

Qualifications

• Bachelor's or Master's degree in Electrical & Electronics Engineering or Computer Engineering.
• Minimum 2 years of Digital IC / RTL Design experience.
• Experience delivering digital IPs from spec to RTL.

Responsibilities

• Lead hardware IP/module development from scratch to SoC integration.
• Derive micro-architecture design specs from system requirements.
• Collaborate with Architecture, Physical Design, and DV teams to meet PPA and timing targets.
• Perform RTL coding, generate timing constraints (SDC), and implement UPF-based low‑power designs.

Skills

RTL Design

CPU Architecture

AMBA Protocols

High‑speed Interfaces

Pre-silicon Simulation

Post-silicon Debug

Pipelining

Timing Optimization

Education

Electrical & Electronics Engineering

Computer Engineering

Job description

XinPal Malaysia seeks a Digital Design Engineer (SoC/IP) in Bayan Lepas, Penang to drive hardware IP development from concept to RTL and final SoC integration. You will collaborate with Architecture, Physical Design, and DV to hit PPA targets and timing constraints.

The role requires a minimum of 2 years' experience in Digital IC/RTL Design and hands-on RTL coding with a strong background in CPU architectures, AMBA protocols, and high-speed interfaces.