Senior ISP & ASIC Design Lead — Imaging

XPENG; Kuala Lumpur; On-site; MYR 180,000 - 240,000; Full time

Job summary

XPENG is seeking an experienced ISP Architect to own the micro-architecture and RTL of core ISP blocks from spec to tape-out, ensuring a smooth ramp to mass production. You will drive PPA trade-offs, dataflow, buffering, and interface design while collaborating with algorithm, tuning, SW/driver, DV and backend teams to align on references and convergence plans.

You will mentor engineers, champion design methodology, low-power strategies, and robust documentation, contributing to the growth of

Qualifications

• BS or above in Microelectronics / EE / Communications / CS or related field.
• 5+ years of digital IC front-end experience with at least one taped-out chip containing ISP as a key contributor or module owner.
• Strong proficiency in Verilog / SystemVerilog and SVA.
• Proficient with mainstream EDA tools; familiar with JasperGold / VC Formal.
• Solid experience with AMBA protocols and high-bandwidth DMA design.
• Deep understanding of the full camera imaging pipeline and hardware implications.
• In-depth knowledge of mainstream CFA patterns and their hardware implications.
• Strong engineering intuition for ISP bandwidth, line-buffer area and power budgets.
• Proven ability to drive technical discussions with algorithm engineers on precision, approximation and hardware-friendliness.

Responsibilities

• Own the micro-architecture and RTL of key ISP blocks or sub-systems end-to-end from spec through tape-out.
• Lead pipeline-level dataflow, buffering strategy and interface design; manage PPA trade-offs.
• Collaborate with algorithm, tuning, SW/driver, DV and backend teams on reference-model strategy and interfaces.
• Lead silicon-stage image-quality debug, root-cause analysis and RTL ECOs; ensure ramp to mass production.
• Mentor mid-level and junior engineers; drive design methodology, code quality, low-power and documentation standards.

Skills

Verilog / SystemVerilog

SVA

EDA tools

JasperGold

VC Formal

AMBA protocols

DMA design

Camera imaging pipeline

CFA patterns

ISP bandwidth

Technical leadership

Education

Bachelor’s degree or above in Microelectronics / EE / CS / related

Tools

JasperGold

VC Formal

Job description

XPENG is seeking an experienced ISP Architect to own the micro-architecture and RTL of core ISP blocks from spec to tape-out, ensuring a smooth ramp to mass production. You will drive PPA trade-offs, dataflow, buffering, and interface design while collaborating with algorithm, tuning, SW/driver, DV and backend teams to align on references and convergence plans.

You will mentor engineers, champion design methodology, low-power strategies, and robust documentation, contributing to the growth of