Turing Chip Project- Senior Staff ASIC Design Engineer(A139091)

XPENG; Kuala Lumpur; Vor Ort; MYR 180.000 - 240.000; Vollzeit

Zusammenfassung

XPENG is seeking an experienced ISP Architect to own the micro-architecture and RTL of core ISP blocks from spec to tape-out, ensuring a smooth ramp to mass production. You will drive PPA trade-offs, dataflow, buffering, and interface design while collaborating with algorithm, tuning, SW/driver, DV and backend teams to align on references and convergence plans.

You will mentor engineers, champion design methodology, low-power strategies, and robust documentation, contributing to the growth of

Qualifikationen

• BS or above in Microelectronics / EE / Communications / CS or related field.
• 5+ years of digital IC front-end experience with at least one taped-out chip containing ISP as a key contributor or module owner.
• Strong proficiency in Verilog / SystemVerilog and SVA.
• Proficient with mainstream EDA tools; familiar with JasperGold / VC Formal.
• Solid experience with AMBA protocols and high-bandwidth DMA design.
• Deep understanding of the full camera imaging pipeline and hardware implications.
• In-depth knowledge of mainstream CFA patterns and their hardware implications.
• Strong engineering intuition for ISP bandwidth, line-buffer area and power budgets.
• Proven ability to drive technical discussions with algorithm engineers on precision, approximation and hardware-friendliness.

Aufgaben

• Own the micro-architecture and RTL of key ISP blocks or sub-systems end-to-end from spec through tape-out.
• Lead pipeline-level dataflow, buffering strategy and interface design; manage PPA trade-offs.
• Collaborate with algorithm, tuning, SW/driver, DV and backend teams on reference-model strategy and interfaces.
• Lead silicon-stage image-quality debug, root-cause analysis and RTL ECOs; ensure ramp to mass production.
• Mentor mid-level and junior engineers; drive design methodology, code quality, low-power and documentation standards.

Kenntnisse

Verilog / SystemVerilog

SVA

EDA tools

JasperGold

VC Formal

AMBA protocols

DMA design

Camera imaging pipeline

CFA patterns

ISP bandwidth

Technical leadership

Ausbildung

Bachelor’s degree or above in Microelectronics / EE / CS / related

Tools

JasperGold

VC Formal

Jobbeschreibung

Responsibilities

• 1.ISP Module / Sub-System Ownership：Own the micro-architecture and RTL of key ISP blocks or sub-systems end-to-end, from spec definition through tape-out and mass production.
• 2.Architecture & PPA Leadership：Drive pipeline-level dataflow, buffering strategy and interface design; lead PPA trade-offs across image quality, area, bandwidth and power; deliver architecture and μArch specifications.
• 3.Cross-Team Collaboration：Partner deeply with algorithm, tuning, SW / driver, DV and backend teams; align on reference-model strategy, register interfaces and convergence plans.
• 4.Silicon Bring-up & Productization：Lead silicon-stage image-quality debug, root-cause analysis and RTL ECOs; ensure smooth ramp to mass production.
• 5.Technical Leadership：Mentor mid-level and junior engineers; drive design methodology, code quality, low-power (UPF), CDC / RDC and documentation standards across the team.

Requirements

Basic

• 1.BS or above in Microelectronics / EE / Communications / CS or related field.
• 2.5+ years of digital IC front-end experience, with at least one taped-out chip containing ISP as a key contributor or module owner.
• 3.Strong proficiency in Verilog / SystemVerilog and SVA.
• 4.Proficient with mainstream EDA tools; familiar with JasperGold / VC Formal.
• Solid experience with AMBA protocols and high-bandwidth DMA design.
• 5.Deep understanding of the full camera imaging pipeline; able to articulate the physical meaning, image-quality impact and hardware implementation of each stage.
• 6.In-depth knowledge of mainstream CFA patterns and their hardware implications.
• 7.Strong engineering intuition for ISP bandwidth, line-buffer area and power budgets.
• 8.Proven ability to drive technical discussions with algorithm engineers on precision, approximation and hardware-friendliness.

Nice to Have

• 1.Hands-on experience with AI-ISP HW/SW co-design.
• 2.Experience with multi-camera fusion, bokeh, super-resolution or similar advanced imaging features.
• 3.Automotive ISP experience.
• 4.Familiarity with MIPI CSI-2 and a broad range of sensor RAW characteristics.
• 5.Track record of leading a module from spec to sign-off.
• 6.Experience with commercial ISP IP or in-house ISP development.

XPENG offers

• An interesting, unique and very varied job at XPENG
• A job with an incredibly large contact surface both internally and externally
• An attractive salary package incl. pension and with the possibility of a bonus
• To be involved in the growth of an existing EV brand in Europe

Next steps

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As part of our application process, certain positions at our company require a pre-employment screening to ensure the reliability and integrity of our employees. This screening is a standard procedure and may include components such as a Criminal Background Check from your current or previous country of residence over the past five years. Additionally, the process may involve an integrity questionnaire, verification of identification, diplomas, work experience, and consultation of the central insolvency register.

We appreciate your understanding and cooperation in this important matter, as it helps us maintain the high standards expected by our team.

Our Commitment to Diversity and Inclusion

At XPENG, we’re an equal-opportunity employer that values diversity and positively encourages applications from suitably qualified and eligible candidates regardless of race, religion, sex, national origin, gender, sexual orientation, age, marital status, disability status or other applicable legally protected characteristics.