Senior RTL Design Engineer for ASIC/VLSI

Bitdeer (NASDAQ: BTDR)

Penang

On-site

MYR 80,000 - 180,000

Full time

14 days+
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Job summary

Bitdeer is seeking an experienced RTL Design Engineer in Penang, Malaysia to contribute to ASIC design using Verilog HDL. You will participate in architectural discussions, perform RTL coding, and support design reviews, ensuring quality from specification to tape-out.

You will collaborate with verification, emulation and implementation teams, apply strong computer architecture and VLSI knowledge, and work on GPGPU/NPU/CPU modules.

Qualifications

  • RTL design experience on ASIC with tape-out experience.
  • Strong understanding of computer architecture and VLSI design.
  • Experience in GPGPU/NPU/CPU module design including work scheduler, memory subsystem, vector processor core, tensor processor core.

Responsibilities

  • Participated in architectural design discussions.
  • Microarchitectural design and implementation using Verilog HDL based on the architectural specifications.
  • Design reviews and delivery quality control.
  • Soft and hard IP identification, selection and integration
  • Collaboration with verification and emulation teams in test plan development and debug
  • Collaboration with implementation team to close the design on synthesis, timing and power.

Education

Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, Computer Science, or related fields.

Tools

Verilog HDL

Job description

Bitdeer is seeking an experienced RTL Design Engineer in Penang, Malaysia to contribute to ASIC design using Verilog HDL. You will participate in architectural discussions, perform RTL coding, and support design reviews, ensuring quality from specification to tape-out.

You will collaborate with verification, emulation and implementation teams, apply strong computer architecture and VLSI knowledge, and work on GPGPU/NPU/CPU modules.

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