Senior Physical Design Engineer – CPU PPA Optimization

AheadComputing Inc.; Región Centro; Presencial; MXN 600.000 - 800.000; Jornada completa

Ventajas ofrecidas por este puesto de trabajo

Competitive salary and benefits package

Opportunities for professional growth

Flexible and inclusive work culture

Descripción de la vacante

A technology startup in Guadalajara, Mexico is looking for a Physical Design Engineer to optimize CPU power, performance, and area (PPA). The role involves physical implementation from RTL-to-GDSII, working closely with RTL designers to enhance efficiency. Candidates should have a degree in engineering, over 4 years of experience, and proficiency in EDA tools like Synopsys or Cadence. The position offers competitive salary, professional growth opportunities, and a flexible work culture.

Formación

• 4+ years of experience in physical design of complex ASICs or CPUs.
• Strong expertise in tool flows and PPA trade-offs.
• Hands-on experience with power analysis and leakage optimization.

Responsabilidades

• Own physical implementation of CPU blocks from RTL-to-GDSII.
• Utilize back-end EDA tool flows for timing closure.
• Optimize floorplanning and power delivery networks.

Conocimientos

Physical Design methodologies

PPA trade-offs

Scripting skills in Python

Experience with EDA tools

Problem-solving skills

Educación

Bachelor’s/Master’s/PhD in Electrical Engineering or Computer Engineering

Herramientas

Synopsys tools (ICC2, Design Compiler, PrimeTime)

Cadence tools (Innovus, Genus, Tempus)

Descripción del empleo

We are seeking a Physical Design Engineer to drive CPU power, performance, and area (PPA) optimization at advanced technology nodes. You will be responsible for physical implementation, collaborating with RTL, and logic design teams to deliver high-performance, and power-efficient processors.

Responsibilities

• Own and drive physical implementation of CPU blocks from RTL-to-GDSII, focusing on PPA trade-offs.
• Utilize back-end EDA tool flows, develop/optimize methodologies for synthesis, place-and-route (PnR), clock tree synthesis (CTS), and timing closure.
• Work closely with RTL designers to improve timing, area and power efficiency, and evaluate design changes and their impact on PPA.
• Perform static timing analysis (STA), power analysis, signal integrity checks, and DFT implementation.
• Optimize floorplanning, clock distribution, power delivery networks, and congestion reduction strategies.
• Automate design flows and methodologies to improve efficiency and scalability.

Minimum Qualifications

• Bachelor’s/Master’s/PhD in Electrical Engineering, Computer Engineering, or related field.
• 4+ years of experience in physical design of complex ASICs or CPUs.
• Strong expertise in Physical Design methodologies, tool flows, and PPA trade-offs.
• Proficiency with EDA tools such as Synopsys (ICC2, Design Compiler, PrimeTime), or Cadence (Innovus, Genus, Tempus).
• Solid knowledge of place-and-route, clock tree synthesis, timing closure, and physical verification.
• Hands‑on experience with power analysis, leakage optimization, ECO implementation and equivalence sign‑off.
• Proficiency in reading RTL (Verilog/VHDL) and understanding logic design.
• Strong scripting skills in Python, Tcl, or Perl for tool automation and data analysis.
• Excellent problem‑solving skills and ability to work in a cross‑functional team environment.

Preferred Qualifications

• Experience in advanced process nodes (5nm, 3nm, or below).
• Understanding of low‑power design techniques such as clock gating, power gating, multi‑Vt optimization and multi‑power domain.
• Knowledge of DFT, multi‑corner multi‑mode (MCMM) constraints, and sign‑off flows.

What We Offer

• Competitive salary and benefits package.
• Opportunities for professional growth in an innovative startup environment.
• Collaboration with talented engineers passionate about cutting‑edge CPU technologies.
• A flexible and inclusive work culture based in Guadalajara, Mexico.