Physical Design Engineer

AheadComputing Inc.; Región Centro; Presencial; MXN 500.000 - 800.000; Jornada completa

Ventajas ofrecidas por este puesto de trabajo

Competitive salary and benefits package

Opportunities for professional growth

Flexible and inclusive work culture

Descripción de la vacante

A technology company is seeking a Physical Design Engineer in Guadalajara, Mexico, to optimize CPU power, performance, and area. Responsibilities include managing physical implementation from RTL to GDSII, working with RTL designers on timing and power efficiency, and utilizing advanced EDA tool flows. Candidates should have a degree in Electrical Engineering and expertise in physical design methodologies. The position offers a competitive salary and opportunities for professional growth in an innovative environment.

Formación

• 1+ years of experience in physical design of complex ASICs or CPUs.
• Solid knowledge of place-and-route and physical verification.
• Hands-on experience with power analysis and leakage optimization.

Responsabilidades

• Drive physical implementation of CPU blocks focusing on PPA trade-offs.
• Develop/optimize methodologies for synthesis and timing closure.
• Automate design flows to improve efficiency.

Conocimientos

Physical Design methodologies

EDA tools

Scripting in Python

Problem-solving

Educación

Bachelor’s/Master’s/PhD in Electrical Engineering

Herramientas

Synopsys (ICC2, Design Compiler, Prime Time)

Cadence (Innovus, Genus, Tempus)

Descripción del empleo

We are seeking a Physical Design Engineer to drive CPU power, performance, and area (PPA) optimization at advanced technology nodes. You will be responsible for physical implementation, collaborating with RTL, and logic design teams to deliver high-performance, and power-efficient processors.

Responsibilities

• Own and drive physical implementation of CPU blocks from RTL-to-GDSII, focusing on PPA trade-offs.
• Utilize back-end EDA tool flows, develop/optimize methodologies for synthesis, place-and-route (PnR), clock tree synthesis (CTS), and timing closure.
• Work closely with RTL designers to improve timing, area and power efficiency, and evaluate design changes and their impact on PPA.
• Perform static timing analysis (STA), power analysis, signal integrity checks, and DFT implementation.
• Optimize floorplanning, clock distribution, power delivery networks, and congestion reduction strategies.
• Automate design flows and methodologies to improve efficiency and scalability.

Qualifications

• Bachelor’s/Master’s/PhD in Electrical Engineering, Computer Engineering, or related field.
• 1+ years of experience in physical design of complex ASICs or CPUs.
• Strong expertise in Physical Design methodologies, tool flows, and PPA trade-offs.
• Proficiency with EDA tools such as Synopsys (ICC2, Design Compiler, Prime Time), or Cadence (Innovus, Genus, Tempus).
• Solid knowledge of place-and-route, clock tree synthesis, timing closure, and physical verification.
• Hands‑on experience with power analysis, leakage optimization, ECO implementation and equivalence signoff.
• Proficiency in reading RTL (Verilog/VHDL) and understanding logic design.
• Strong scripting skills in Python, Tcl, or Perl for tool automation and data analysis.
• Excellent problem‑solving skills and ability to work in a cross‑functional team environment.

Benefits

• Competitive salary and benefits package.
• Opportunities for professional growth in an innovative startup environment.
• Collaboration with talented engineers passionate about cutting‑edge CPU technologies.
• A flexible and inclusive work culture based in Guadalajara, Mexico.