CPU Pre-Silicon Verification Engineer

Intel Corporation; Región Centro; Presencial; MXN 892.800 - 1.339.200; Jornada completa

Descripción de la vacante

Intel Corporation is looking for a highly motivated Senior CPU Pre-Silicon Verification Engineer to enhance their CPU verification team. This role is centered on ensuring the correctness of CPU logic designs using cutting-edge verification methodologies.

The ideal candidate will lead the verification of complex CPU architectures, develop comprehensive verification plans, and work closely with architects and designers. Strong skills in scripting, C++, and SystemVerilog are essential, along with a Bachelor's degree in an engineering field and fluency in English.

Formación

• 5+ years of experience in digital logic design or 3+ years with a Master's degree.
• Experience in instruction set execution, ALUs, control units, registers, memory, and buses.
• Strong analytical skills and creative problem solving.

Responsabilidades

• Lead and execute pre-silicon functional verification of CPU microarchitecture.
• Develop verification and test plans including stress scenarios.
• Mentor junior engineers and enhance verification methodologies.

Conocimientos

Proficiency in scripting languages (Python, Perl, Tcl)

C++

SystemVerilog

Analytical and debugging skills

English proficiency

Educación

Bachelor’s or Master’s degree in Electrical/Electronic Engineering or Computer Engineering

Herramientas

Synopsys simulators

Descripción del empleo

We are seeking a highly motivated and experienced Senior CPU Pre‑Silicon Verification Engineer to join our advanced CPU verification team. The role focuses on ensuring the functional correctness and robustness of CPU logic designs through state‑of‑the‑art pre‑silicon verification methodologies.

Responsibilities

• Lead and execute pre‑silicon functional verification of complex CPU microarchitecture blocks and top‑level subsystems, ensuring correctness against architectural and microarchitectural specifications.
• Develop, own, and maintain comprehensive verification and test plans, including corner cases, stress scenarios, and detailed coverage goals.
• Architect, build, and enhance scalable UVM‑based (or similar) constrained‑random verification environments, including reusable testbenches, agents, sequences, checkers, and scoreboards.
• Define and implement advanced functional, code, and assertion coverage models, driving systematic coverage‑driven closure.
• Implement high‑quality stimulus and assertion‑based verification (SVA) to validate complex logic behaviors and corner‑case interactions.
• Execute block‑level and system‑level simulations to uncover design bugs, integration issues, and functional inconsistencies.
• Debug complex RTL and testbench failures, performing thorough root‑cause analysis using simulation tools, waveforms, formal methods, and collaboration with designers.
• Work closely with CPU architects and RTL designers to validate intricate architectural and microarchitectural features, review specifications, identify verification risks, and propose design or methodology improvements.
• Drive technical reviews and document verification strategies, methodologies, and results, ensuring alignment across architecture, design, and verification teams.
• Enhance verification infrastructure and methodologies, enabling higher automation, scalability, and productivity across the team.
• Mentor junior engineers and contribute to best‑practice development, methodology refinement, and tool‑flow improvements.
• Support related activities, including performance modeling, formal verification, emulation, and prototyping, as needed for overall CPU validation.

Qualifications

Minimum Qualifications:

• Bachelor’s degree or higher in Electrical/Electronic Engineering or Computer Engineering (5+ years of experience) or Master’s degree with 3+ years of experience.
• Experience in digital logic design, including instruction set execution, ALUs, control units, registers, memory, and system buses.
• Proficiency in at least one scripting language (e.g., Python, Perl, or Tcl), C++, and SystemVerilog.
• Strong analytical and debugging skills with a creative approach to problem‑solving.
• Advanced English level.
• Unrestricted, permanent right to work in Mexico.

Preferred Qualifications:

• Experience with Synopsys simulators.
• Hands‑on experience developing UVM‑based testbenches for reusable and scalable verification environments.
• Ability to define and implement validation strategies based on architectural and design insights.

Job Type: Experienced Hire
Shift: Shift1 (Mexico)
Primary Location: Mexico, Guadalajara

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.