Power Management Architect

AheadComputing Inc.; Región Centro; Híbrido; MXN 900.000 - 1.300.000; Jornada completa

Descripción de la vacante

AheadComputing Inc. is seeking a senior Power Management Architect to define system-level power management architecture, CPU power states, and coordination across architecture, design, and firmware teams. You will shape PM policies, interfaces, and validation strategies for post-silicon power behavior.

Ideal candidates have extensive ARM PM experience, PSCI familiarity, and a track record coordinating across multiple engineering domains to deliver robust power solutions for advanced SoCs.

Formación

• 7+ years in SoC or CPU power management architecture.
• Experience with ARM CPU PM architecture and PSCI.
• Knowledge of hardware–firmware PM interaction.
• Understanding of system-level power state management.
• Experience coordinating across architecture, design, and firmware teams.

Responsabilidades

• Define system-level power management architecture and operating modes.
• Define CPU and cluster power states and their coordination mechanisms.
• Define reset flow architecture, including cold and warm reset sequencing and reset-power state interactions.
• Define PM policies, sequencing, and state transitions across the platform.
• Define hardware–firmware power management interfaces and compliance expectations.
• Define power management requirements and constraints to guide implementation teams.
• Align architecture, RTL, physical design, thermal, and firmware teams around a coherent PM strategy.
• Support silicon bring-up and post-silicon power behavior validation.

Conocimientos

ARM PM architecture

System-level power management

Cross-functional coordination

Power delivery constraints

Hardware–firmware PM interaction

PSCI & ARM specs

Herramientas

UPF

Descripción del empleo

• Define system-level power management architecture and operating modes
• Define CPU and cluster power states and their coordination mechanisms
• Define reset flow architecture, including cold and warm reset sequencing and reset-power state interactions
• Define PM policies, sequencing, and state transitions across the platform
• Define hardware–firmware power management interfaces and compliance expectations
• Define power management requirements and constraints to guide implementation teams
• Align architecture, RTL, physical design, thermal, and firmware teams around a coherent PM strategy
• Support silicon bring-up and post-silicon power behavior validation

Required Experience

• 7+ years in SoC or CPU power management architecture
• Direct experience with ARM CPU power management architecture, including familiarity with ARM power management specifications and compliance requirements (e.g., PSCI, ARM power state definitions, firmware coordination models)
• Strong understanding of system-level power state management and hardware–firmware PM interaction
• Solid understanding of power delivery constraints
• Track record of cross-functional coordination across architecture, design, and firmware teams

Preferred Experience

• Familiarity with low-power implementation flows (e.g., UPF) and physical power considerations
• Understanding of thermal management concepts and power-thermal interaction at system level
• High-performance or server-class CPU experience
• RISC-V experience
• Silicon bring-up and post-silicon tuning experience
• Multi-generation architecture planning experience