Low Power Design Engineer

North American Production Sharing, Inc.; Tijuana; Presencial; MXN 520.000 - 1.020.000; Jornada completa

Descripción de la vacante

North American Production Sharing, Inc. is seeking a skilled engineer to design adaptive power management controllers, on-chip sensor controllers, and digital power meters for advanced semiconductor SoCs.

You will perform RTL design, simulations, timing analysis, and formal verification, collaborating closely with technology, verification, and system teams. The ideal candidate has 3+ years in low power digital ASIC design, strong Verilog/SystemVerilog skills, and experience with UPF and

Formación

• 3 years of experience doing low power digital ASIC design.

Responsabilidades

• Design adaptive power management controller, on-chip sensor controller, and digital power meter.

Conocimientos

Low power design

RTL coding

SystemVerilog

Verilog

Python scripting

TCL scripting

Power-aware DV

Clocking

Educación

Master's degree in Electrical or Computer Engineering

PhD in Electrical or Computer Engineering

Herramientas

Verilog

SystemVerilog

UPF

Python

Perl

TCL

Descripción del empleo

This position is to work with a global leader company in the design and development of advanced semiconductors, responsible for architectures and platforms that form the core of some of the most innovative devices on the market. Its silicon engineering drives solutions that deliver high performance, energy efficiency, and intelligent integration, complemented by a key role in advancing modern telecommunications through next-generation wireless connectivity technologies. Its solutions are integrated into billions of devices worldwide, offering an ideal professional environment for talent seeking technological impact, innovation, and growth within a global context.

Job Overview:

• Design adaptive power management controller, on-chip sensor controller, and digital power meter.
• Perform RTL design, simulation, synthesis, timing analysis, lint check, clock domain crossing check, conformal low power check, and formal verification for IP blocks.
• Work closely with technology/circuit design team to close IP block specification/requirement.
• Work closely with verification/physical design team to complete the IP design implementation.
• Support SoC team to integrate low power/power management IP solution into wireless SoC chips and front-end design flows.
• Work closely with system/software/test team to enable the low power feature in wireless SoC product.
• Work closely with system/software/test team to enable functional safety feature in automotive SoC product.
• Create/Enhance low power methodologies covering entire design cycle from RTL to GDS. Analyze how a new methodology will affect different phases of the design/verification cycle and work on fixing any issues.
• Provide feedback for low-power chip and system architecture.
• Understand and perform block & chip-level power analysis.
• Understand and create block-level power models.
• 3 years of experience doing low power digital ASIC design.
• Familiar with ASIC front-end design process and related flow, including u-arch, RTL coding, simulation, synthesis, STA.
• Familiar with scripting languages like Python, Perl, TCL.
• Understanding of electrical engineering concepts, circuit analysis, and logic design skills.

Preferred Qualifications:

• Familiarity with advanced low power techniques and tools such as UPF, CLP, power aware DV, and high-speed clocking desired.
• Proficiency in Verilog/System Verilog coding, verification techniques, and scripting languages, such as Perl, Python, Tcl, and Make etc.
• Good understanding of SoC architecture/micro-architecture.
• Understanding of automotive functional safety standard ISO 26262 and analysis technique (FMEA/FMEDA) is a plus.
• Strong debugging capabilities at simulation, emulation, and Silicon environments, including the ability to design interesting debug experiments.
• Collaborate closely with cross-function team to research, design and implement performance and power management strategy for the product roadmap.

Education Requirements:

Masters or PhD in Electrical or Computer Engineering.