Senior SoC Pre-Silicon Verification Engineer

3M HEALTHCARE; Región Centro; Presencial; MXN 600.000 - 900.000; Jornada completa

Descripción de la vacante

3M HEALTHCARE in Guadalajara seeks an experienced verification engineer to perform functional verification of an integrated SoC and develop scalable verification environments. You will execute plans, run emulation models, and collaborate with RTL, architecture, and design teams to ensure coverage and security are embedded in pre-silicon workflows.

Requirements include a 5+ year background in hardware verification with Verilog/VHDL, UVM/SystemVerilog, and strong English proficiency; applicants

Formación

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field with 5+ years of industry experience, or Master's degree with 4+ years of experience.
• 4+ years of experience with hardware description languages such as Verilog or VHDL and verification tools like UVM or SystemVerilog, or relevant experience in silicon validation.
• Experience with simulation or emulation tools, debugging scripts, and functional coverage analysis.
• Advanced English level.
• Unrestricted, permanent right to work in Mexico (no visa or immigration sponsorship available).

Responsabilidades

• Perform functional logic verification of an integrated SoC to meet specifications.
• Define scalable verification plans, test benches, and environments for coverage and microarchitecture specs.
• Execute verification plans; run emulation/system-simulation models to verify design, analyze power and performance.
• Debug issues in pre-silicon environment, implement corrective measures for failing tests.
• Collaborate with SoC architects, RTL developers, and other teams to improve verification of complex features.
• Document test plans and lead technical reviews with design and architecture teams.
• Incorporate security activities within test plans, including regression and debugging tests.
• Maintain and improve existing verification infrastructure and methodology.
• Apply post-silicon learnings to improve pre-silicon validation and update coverage for future products.

Conocimientos

Verilog/SystemVerilog

UVM

Python

C/C++

ARM‑based SoC

Linux/Unix

CI/CD pipelines

Security verification

Regression testing

VCS/Questa/Xcelium

Educación

Bachelor's degree in Electrical Engineering/Computer Engineering/CS

Master's degree (advantageous)

Herramientas

VCS

Xcelium

Questa

UPF

Git/Perforce

Descripción del empleo

Position Overview

This role requires candidates to upload a resume in English and will only consider an English version of the resume.

Responsibilities

• Perform functional logic verification of an integrated SoC to ensure design meets specifications.
• Define and develop scalable and reusable block, subsystem, and SoC verification plans, test benches, and verification environments to achieve required coverage and meet microarchitecture specifications.
• Execute verification plans and run emulation and system‑simulation models to verify design, analyze power and performance, and uncover bugs.
• Replicate, root‑cause, and debug issues in the pre‑silicon environment, and implement corrective measures to resolve failing tests.
• Collaborate and communicate with SoC architects, microarchitects, full chip architects, RTL developers, post‑silicon, and physical design teams to improve verification of complex architectural and microarchitectural features.
• Document test plans and lead technical reviews of plans and proofs with design and architecture teams.
• Incorporate and execute security activities within test plans, including regression and debugging tests, to ensure security coverage.
• Maintain and improve existing functional verification infrastructure and methodology.
• Apply learning from post‑silicon to improve validation quality during pre‑silicon development, update test plans for missing coverage, and propagate lessons to future products.

Qualifications

Minimum Qualifications

• Bachelor’s degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field with 5+ years of industry experience, or Master’s degree with 4+ years of experience.
• 4+ years of experience with hardware description languages such as Verilog or VHDL and verification tools like UVM or SystemVerilog, or relevant experience in silicon validation.
• Experience with simulation or emulation tools, debugging scripts, and functional coverage analysis.
• Advanced English level.
• Unrestricted, permanent right to work in Mexico (no visa or immigration sponsorship available).

Preferred Qualifications

• Advanced academic or professional experience contributing to complex CPU or SoC design projects.
• Passion for innovation and a drive to contribute to industry‑leading solutions.
• 4+ years of SystemVerilog and UVM experience.
• 4+ years of Python for test automation.
• Proficiency in C/C++ and scripting (Perl, Tcl, Shell).
• 2+ years with simulation tools (VCS, Xcelium, Questa).
• Experience with formal verification tools and coverage analysis, constrained random and assertion‑based verification.
• 3+ years of ARM‑based SoC or equivalent architecture experience.
• Knowledge of AMBA protocols (AXI, AHB, APB) and interconnects, memory subsystems, cache coherency, power management.
• Experience with high‑speed interfaces (PCIe, DDR, USB, Ethernet).
• 3+ years of pre‑silicon verification experience.
• Linux/Unix and version control (Git, Perforce) experience.
• Experience with regression testing and CI/CD pipelines.
• Security verification methodologies experience.
• Experience with pre‑silicon functional verification, including planning, debugging, testbench design, UPF and coverage closure.

Job Details

• Job Type: Experienced Hire
• Shift: Shift 1 (Mexico)
• Primary Location: Mexico, Guadalajara
• Additional Locations: Not specified
• Business Group: Data Center Group (DCG)

Equal Employment Opportunity

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.