Clock / Power HW Validation Engineer

North American Production Sharing, Inc.; Tijuana; Presencial; MXN 391.000 - 670.000; Jornada completa

Descripción de la vacante

North American Production Sharing, Inc. in Tijuana, MX, seeks a SoC validation engineer to own end-to-end bare metal validation of clock and power architectures for mobile/server/compute SoCs.

You will plan validation, develop test plans, automate with Python/C, and collaborate across time zones while using lab instruments to debug pre- and post-Si issues.

Formación

• Bachelor’s degree in engineering (electronics, computer engineering, etc.)
• 2+ years in SoC validation or related areas (SW development, embedded)
• Proficient in C, Python
• Experience with lab instruments (multimeter, oscilloscope, logic analyzers)
• Exposure to ARM-based SoC debug and JTAG-based methods

Responsabilidades

• Own end-to-end bare metal framework validation of clock and power architectures for mobile/server/compute SoCs
• Plan validation activities: design changes, test requirements and scenarios
• Develop test plans and document dependencies
• Review validation strategy with architects, designers, verification engineers, software engineers
• Collaborate with teams across different time zones
• Automate validation processes using Python, Perl, shell
• Develop device drivers and tests in C for platform validation
• Review validation platform schematics for post-Si debug support
• Utilize lab instruments for measurements and debugging
• Debug complex issues on pre-Si and post-Si platforms

Conocimientos

C language

Python

SoC validation

Embedded systems

JTAG

Educación

Bachelor’s degree in engineering

Herramientas

Verilog

SystemVerilog

Cross-compilers

Makefiles

Descripción del empleo

This position is to work with a global leader company in the design and development of advanced semiconductors, responsible for architectures and platforms that form the core of some of the most innovative devices on the market. Its silicon engineering drives solutions that deliver high performance, energy efficiency, and intelligent integration, complemented by a key role in advancing modern telecommunications through next-generation wireless connectivity technologies. Its solutions are integrated into billions of devices worldwide, offering an ideal professional environment for talent seeking technological impact, innovation, and growth within a global context.

• Own the E2E bare metal framework validation of mobile/ server/ compute SoC clock and power architectures
• Validation planning – understand design changes, visualize standalone and system level test requirements and scenarios
• Test plan development – clearly document test strategy and dependencies
• Conduct validation strategy and test plan review with all stakeholders – architects, designers, verification engineers, software engineers
• Efficiently collaborate with teams in different time zones – both internal and external
• Automate validation process – development, execution, inference using python, perl, shell
• Develop scalable device drivers, standalone and system tests using C
• Review validation platform schematics to ensure post-Si debug support – might have to work with platform design team
• Use lab instruments – multimeter, oscilloscopes , logic analyzers
• Debug complex issues both on pre-Si and post-Si platforms, provide debug direction

What you'll need:

• Mandatory:
  • Bachelor’s degree in engineering (electronics, computer engineering etc.)
  • 2+ years of relevant experience in SoC validation and / or associated areas (SW development, embedded systems etc.)
  • Prior work experience in clock/ power validation
  • Proficient in C, Python
  • Experienced in using lab instruments – multimeter, oscilloscopes , logic analyzers
  • Exposure to debug tools (JTAG etc.). Knowledge of debug methodology of ARM based SoCs
  • Very good at problem solving - analytical and debugging skills
• Plus:
  • Prior exposure to below SW skills would add an edge above other applicants:
    • Experience with Cross-Compilers, Linkers and makefiles
    • Understanding of coherency and concurrency in modern SoC architectures
  • Knowledge of PMIC/ prior experience in validating rail power (power measurement tools/ setups)
  • Knowledge of pre-Silicon validation and debug on FPGA based emulation platforms is a plus
  • Knowledge of RTL and HDLs (Verilog/ System Verilog) would be an additional advantage
  • Should have prior work experience in a cross functional matrix work environment