SoC Design & Synthesis Engineer

North American Production Sharing, Inc.; Tijuana; Presencial; MXN 600.000 - 900.000; Jornada completa

Descripción de la vacante

North American Production Sharing, Inc. seeks an ASIC design engineer to synthesize large-scale SoC RTL into gate-level netlists and own multi-stage synthesis flows, ensuring PD handoff readiness.

You will optimize PPA, analyze timing constraints (SDC), and support functional ECOs while collaborating with Design, DFT, and Physical Design teams to deliver robust, manufacturable Snapdragon-class designs. Frontend experience in ASIC design and strong debugging, scripting, and execution under tight

Formación

• Bachelor's degree in Science, Engineering, or related field; 2+ years ASIC design experience.
• Master's degree or PhD with related ASIC design/verification experience.
• Experience with gate-level netlist quality checks and PD-ready handoffs.
• Strong knowledge of timing constraints (SDC) across functional and test modes.
• Ability to analyze and optimize PPA trade-offs.
• Experience supporting functional ECOs and validating correctness.
• Excellent debugging and analytical thinking under tight project schedules.

Responsabilidades

• Own synthesis inputs and execute multi-stage synthesis flows.
• Ensure netlist quality with respect to timing, power, and DFT before PD handoff.
• Contribute to PPA optimization by analyzing trade-offs and recommending improvements.
• Work with Design, DFT, and Physical Design teams to resolve issues early in the flow.
• Support functional ECOs and validate post-change correctness.
• Document IP development and enable robust, manufacturable designs.

Conocimientos

gate-level netlist checks

PD-ready handoffs

timing constraints (SDC)

PPA optimization

functional ECOs

debugging & analysis

synthesis flow execution

tight schedules

ASIC design experience

scripting languages

Educación

Bachelor's degree in Science, Engineering, or related field

Master's degree in Science, Engineering, or related field

PhD in Science, Engineering, or related field

Herramientas

RTL to GDS Flow

Virtuoso

Python scripting

EDA tools

Spice simulations

Descripción del empleo

This role focuses on synthesizing large ‑ scale SoC RTL designs into high ‑ quality gate ‑ level netlists that are ready for Place & Route. Responsibilities include owning all synthesis inputs, executing multi ‑ stage synthesis flows, and ensuring netlist quality with respect to timing, power, and DFT requirements prior to Physical Design handoff.

The role also contributes to PPA (Power, Performance, Area) optimization by analyzing trade ‑ offs and recommending design or constraint improvements, while working closely with Design, DFT, and Physical Design teams to resolve issues early in the flow. In addition, the engineer supports functional ECOs and validates post ‑ change correctness to improve functionality and fix late ‑ stage issues, ensuring timely delivery of robust, manufacturable designs used in Snapdragon products across mobile, automotive, and edge AI platforms.

Required Skills

• Experience with gate ‑ level netlist quality checks and PD‑ready handoffs
• Solid knowledge of timing constraints (SDC) across functional and test modes
• Ability to analyze and optimize PPA (Power, Performance, Area) trade‑offs
• Experience supporting or implementing functional ECOs and validating correctness
• Effective debugging, analytical thinking, and execution under tight project schedules

Minimum Qualifications:

• Bachelor's degree in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience. or
  Master's degree in Science, Engineering, or related field and 1+ year of ASIC design, verification, validation, integration, or related work experience. or
  PhD in Science, Engineering, or related field.

Preferred Qualifications:

Master\'s degree inElectrical/ElectronicEngineering, Computer Engineering, or Computer Science.

3+ years of ASIC design, verification, validation, integration, or related work experience.
2+ years of experience with architecture and design tools.
2+ years of experience with scripting tools and programming languages.

2+ years of experience with design verification methods.

Applies ASIC knowledge and experience to define, model, design (digital and/or analog), optimize, verify, validate, implement, and document IP (block/SoC) development for a variety of high performance, high quality, low power products.

Creates architectures, circuit specifications, logic designs, and/or system simulations based on system-level requirements.

Collaborates across teams (e.g., software architecture, hardware architecture) to develop and execute an implementation strategy that meets system requirements and customer needs.

Evaluates all aspects of process flow from high-level design to synthesis, place and route, timing and power use, and verification or similarly for custom circuit design/layout flow.

Utilizes tools/applications (e.g., RTL to GDS Flow, Virtuoso) to execute and enable architecture and design of an individual block/SoC or IC Package.

Writes detailed technical documentation for EDA/IP/ASIC projects.