SoC Physical Design Engineer: Power, Timing & Automation

Nokia; Bardi; Ibrido; EUR 90.000 - 120.000; Tempo pieno

Vantaggi offerti da questo lavoro

Flexible and hybrid working schemes

Parental leave (90 days) with return

Life insurance for employees

Well-being programs for mental and физ

Participation in Nokia Employee Rule (

Descrizione del lavoro

Nokia in Italy is seeking an experienced SoC Physical Design Engineer to drive physical design for Optical Network ASICs across 3/5/7nm nodes, focusing on power, performance, and area. You will perform floorplanning, place & route, and timing closure, collaborate with logic designers and hardware teams, and develop PD methodologies and automation scripts from Synthesis to GDSII.

The role values problem solving, analytical mindset, and strong teamwork, with flexible/hybrid working schemes and

Competenze

• 3+ years of experience in ASIC physical design flow and methodologies on 3/5/7nm nodes.
• Solid knowledge of RTL to GDSII and IC design concepts.
• Experience with EDA tools: Fusion Compiler or Innovus, Primetime or equivalent, Calibre, Redhawk.
• Scripting in TCL, Python or Perl.

Mansioni

• Perform floorplanning, place & route, and power/clock distribution for blocks and full chips.
• Execute physical verification, IR/EM analysis, and timing closure at block and chip level.
• Collaborate with logic designers and hardware teams on feasibility studies and design trade-offs.
• Evaluate IP vendors, process nodes, and provide actionable recommendations.
• Develop PD methodologies and automation scripts for steps from Synthesis to GDSII.
• Conduct static timing analysis, create timing constraints, validate critical paths, and sign off timing.

Conoscenze

Floorplanning & P&R

Timing closure

RTL to GDSII knowledge

Collaboration

Analytical mindset

Problem solving

Formazione

Bachelor's degree in Electrical / Electronics / VLSI

Strumenti

Fusion Compiler

Innovus

Primetime

Calibre

Redhawk

Descrizione del lavoro

Nokia in Italy is seeking an experienced SoC Physical Design Engineer to drive physical design for Optical Network ASICs across 3/5/7nm nodes, focusing on power, performance, and area. You will perform floorplanning, place & route, and timing closure, collaborate with logic designers and hardware teams, and develop PD methodologies and automation scripts from Synthesis to GDSII.

The role values problem solving, analytical mindset, and strong teamwork, with flexible/hybrid working schemes and