SoC Physical Design Engineer: Floorplanning, Timing & Automation

Nokia; La Spezia; Ibrido; EUR 70.000 - 100.000; Tempo pieno

Vantaggi offerti da questo lavoro

Flexible & hybrid work

Parental leave 90 days

Life insurance

Well-being programs

NERGs

Career development

Descrizione del lavoro

Nokia seeks an experienced ASIC physical design engineer to implement floorplanning, place & route, and power/clock distribution for submicron nodes. You will work with a hardware/RTL team to translate designs into silicon and optimize flows.

This role emphasizes collaboration across cross-functional teams, verification rigor, and automation, with hybrid work and strong learning opportunities in latest nodes and tools.

Competenze

• 3+ years of experience in ASIC physical design flow and methodologies on 3/5/7nm nodes.
• Strong knowledge of RTL to GDSII and IC design concepts.
• Experience with EDA tools: Fusion Compiler or Innovus, Primetime or equivalent, Calibre, Redhawk.
• Scripting experience in TCL, Python or Perl.
• Bachelor's degree or higher in Electrical/Electronics and Communication/VLSI/Microelectronics.

Mansioni

• Perform floorplanning, placement, routing, and power/clock distribution for blocks and full chips.
• Execute physical verification, IR/EM analysis, and timing closure at block and chip level.
• Collaborate with logic designers and hardware teams on feasibility studies and design trade-offs.
• Evaluate IP vendors and process nodes, providing actionable recommendations.
• Develop PD methodologies and automation scripts for steps from Synthesis to GDSII.
• Conduct static timing analysis and sign off timing.

Conoscenze

Floorplanning

Place & Route

Timing analysis

Scripting TCL/Python/Perl

Cross-functional collaboration

Analytical mindset

Problem solving

RTL to GDSII knowledge

Formazione

Bachelor's degree or higher in Electrical/Electronics and Communication/VLSI/Microelectronics

Strumenti

Fusion Compiler

Innovus

Primetime

Calibre

Redhawk

Descrizione del lavoro

Nokia seeks an experienced ASIC physical design engineer to implement floorplanning, place & route, and power/clock distribution for submicron nodes. You will work with a hardware/RTL team to translate designs into silicon and optimize flows.

This role emphasizes collaboration across cross-functional teams, verification rigor, and automation, with hybrid work and strong learning opportunities in latest nodes and tools.