SoC Physical Design Engineer – Hybrid Work, 3nm+ ASICs

Nokia; Puglia; Ibrido; EUR 65.000 - 95.000; Tempo pieno

Vantaggi offerti da questo lavoro

Flexible/hybrid working schemes

Parental leave

Life insurance

Well-being programs

NERGs

Career development and mentoring

Descrizione del lavoro

Nokia in Bari, Puglia is seeking a SoC Physical Design Engineer to drive floorplanning, placement, routing, and timing closure for cutting-edge Optical Network ASICs. You will translate RTL to GDSII, optimize power, performance and area, and collaborate with logic/design teams on feasibility and trade-offs.

The role demands 3+ years in ASIC physical design on 3/5/7nm nodes, strong scripting (Python/TCL) and experience with Fusion Compiler or Innovus, Primetime, Calibre, and Redhawk.

Competenze

• 3+ years of experience in ASIC physical design flow and methodologies on 3/5/7nm nodes.
• Solid knowledge of RTL to GDSII and underlying IC design concepts.

Mansioni

• Perform floorplanning, place & route, and power/clock distribution for blocks and full chips.
• Execute physical verification, IR/EM analysis, and timing closure at block and chip level.
• Collaborate with logic designers and hardware teams on feasibility studies and design trade-offs.
• Evaluate IP vendors, process nodes, and provide actionable recommendations.
• Develop PD methodologies and automation scripts for steps from Synthesis to GDSII.
• Conduct static timing analysis, create timing constraints, validate critical paths, and sign off timing.

Conoscenze

Team collaboration

Analytical mindset

Problem solving

Floorplanning

Placement/Routing

Formazione

Bachelor's degree or higher in Electrical/Electronics and Communication/VLSI/Microelectronics

Strumenti

Fusion Compiler

Innovus

Primetime

Calibre

Redhawk

Descrizione del lavoro

Nokia in Bari, Puglia is seeking a SoC Physical Design Engineer to drive floorplanning, placement, routing, and timing closure for cutting-edge Optical Network ASICs. You will translate RTL to GDSII, optimize power, performance and area, and collaborate with logic/design teams on feasibility and trade-offs.

The role demands 3+ years in ASIC physical design on 3/5/7nm nodes, strong scripting (Python/TCL) and experience with Fusion Compiler or Innovus, Primetime, Calibre, and Redhawk.