Soc Physical Design Engineer

Nokia; Toscana; Ibrido; EUR 70.000 - 100.000; Tempo pieno

Vantaggi offerti da questo lavoro

Hybrid work

Parental leave

Life insurance

Well-being programs

NERGs

Career development

Descrizione del lavoro

Nokia is seeking a SoC Physical Design Engineer in Livorno, Toscana, Italy to implement physical design for Optical Network ASICs. You will handle floorplanning, placement, routing, and timing closure while collaborating with RTL and hardware teams and driving PD methodologies across 3/5/7nm nodes.

The role emphasizes automation, verification rigor, and learning the latest nodes and tools, with flexible hybrid working arrangements and career development opportunities.

Competenze

• 3+ years of ASIC physical design experience on 3/5/7nm nodes.
• Solid RTL to GDSII knowledge and IC design concepts.
• Experience with EDA tools and scripting (TCL, Python, Perl).

Mansioni

• Perform floorplanning, placement, routing for blocks and full chips.
• Execute physical verification, IR/EM analysis, and timing closure.
• Collaborate with logic designers and hardware teams on feasibility and trade-offs.
• Evaluate IP vendors and process nodes with actionable recommendations.
• Develop PD methodologies and automation scripts from Synthesis to GDSII.

Conoscenze

ASIC physical design

Floorplanning

Place and route

Timing closure

RTL to GDSII

TCL scripting

Python scripting

Team collaboration

Problem solving

Formazione

B.S. in EE/EC

Strumenti

Fusion Compiler

Innovus

Primetime

Calibre

Redhawk

Descrizione del lavoro

In this role, you will implement physical design for Optical Network ASICs across cutting-edge nodes, focusing on power, performance, and area. You will work within a hardware/RTL team to translate designs into silicon and optimize flows for submicron processes. You’ll tackle floorplanning, placement, routing, and timing closure, shaping multi-project IP and design methodologies. The opportunity centers on delivering best-in-class silicon while learning the latest nodes and tools. You will contribute to a mission-driven environment that values automation and rigorous verification.

• Flexible and hybrid working schemes
• Parental leave (90 days) with return option
• Life insurance for employees
• Well-being programs for mental and physical health
• Participation in Nokia Employee Resource Groups (NERGs)
• Career development and coaching/mentoring
• Perform floorplanning, place & route, and power/clock distribution for blocks and full chips
• Execute physical verification, IR/EM analysis, and timing closure at block and chip level
• Collaborate with logic designers and hardware teams on feasibility studies and design trade-offs
• Evaluate IP vendors, process nodes, and provide actionable recommendations
• Develop PD methodologies and automation scripts for steps from Synthesis to GDSII
• Conduct static timing analysis, create timing constraints, validate critical paths, and sign off timing
• 3+ years of experience in ASIC physical design flow and methodologies on 3/5/7nm nodes
• Solid knowledge of RTL to GDSII and underlying IC design concepts
• Experience with EDA tools: Fusion Compiler or Innovus, Primetime or equivalent, Calibre, Redhawk
• Scripting experience in TCL, Python or Perl
• Bachelor's degree or higher in Electrical/Electronics and Communication/VLSI/Microelectronics
• Strong collaboration with cross-functional teams
• team collaboration
• analytical mindset
• problem solving
• Floorplanning and placement/routing

SoC Physical Design Engineer livorno, toscana, it