SoC Physical Design Engineer — Hybrid Work, Cutting-Edge Nodes

Nokia; Catania; Ibrido; EUR 70.000 - 100.000; Tempo pieno

Vantaggi offerti da questo lavoro

Parental leave

Life insurance

Well-being programs

NERGs

Career development

Descrizione del lavoro

Nokia in Italy seeks a SoC Physical Design Engineer in Catania to advance PD for Optical Network ASICs across 3/5/7nm nodes. You will floorplan, place and route, and manage power/clock distribution, while driving RTL-to-GDSII flows.

You will verify timing at block and chip level, collaborate with logic designers, and develop PD methodologies with automation scripts for Synthesis to GDSII. Hybrid work available.

Competenze

• 3+ years of experience in ASIC physical design flow and methodologies on 3/5/7nm nodes.
• Solid knowledge of RTL to GDSII and underlying IC design concepts.
• Experience with EDA tools: Fusion Compiler, Innovus, Primetime, Calibre, Redhawk.
• Scripting experience in TCL, Python or Perl.
• Bachelor's degree or higher in Electrical/Electronics and Communication/VLSI/Microelectronics.

Mansioni

• Perform floorplanning, place & route, and power/clock distribution for blocks and full chips.
• Execute physical verification, IR/EM analysis, and timing closure at block and chip level.
• Collaborate with logic designers and hardware teams on feasibility studies and design trade-offs.
• Evaluate IP vendors, process nodes, and provide actionable recommendations.
• Develop PD methodologies and automation scripts for steps from Synthesis to GDSII.
• Conduct static timing analysis, create timing constraints, validate critical paths, and sign off timing.

Conoscenze

Collaboration

Team collaboration

Analytical mindset

Problem solving

Formazione

Bachelor's degree or higher in Electrical/Electronics and Communication/VLSI/Microelectronics

Strumenti

Fusion Compiler

Innovus

Primetime

Calibre

Redhawk

TCL scripting

Python scripting

Perl scripting

Descrizione del lavoro

Nokia in Italy seeks a SoC Physical Design Engineer in Catania to advance PD for Optical Network ASICs across 3/5/7nm nodes. You will floorplan, place and route, and manage power/clock distribution, while driving RTL-to-GDSII flows.

You will verify timing at block and chip level, collaborate with logic designers, and develop PD methodologies with automation scripts for Synthesis to GDSII. Hybrid work available.