Senior Design Verification Engineer - Data Fabric Systems

Luxoft; Roma; On-site; EUR 50,000 - 70,000; Full time

Job summary

A leading IT consulting firm is seeking a Senior Design Verification Engineer to join their team in Rome. In this role, you'll focus on verifying advanced interconnect systems in state-of-the-art microprocessors. The ideal candidate will have at least 5 years of experience in Digital Design Verification, strong skills in SystemVerilog and UVM, and familiarity with functional verification tools. This is a full-time position offering the opportunity to work on cutting-edge technology.

Qualifications

• Minimum of 5 years experience in Digital Design Verification.
• Strong skills with SystemVerilog and UVM; good skills with Verilog.
• Exposure to both maintaining an existing Verification Environment and creating one from scratch.
• Experience with functional verification tools such as VCS, Cadence, and Mentor Graphics.
• Experience working in a Unix/Linux environment.

Responsibilities

• Perform pre-Silicon Verification of next-generation high-performance Microprocessor designs and related IPs.
• Develop, document, and execute verification test plans at the unit level of design hierarchy.
• Develop high-level language testbench components including stimulus drivers, behavioral models, monitors, and checkers in SystemVerilog.
• Develop, simulate, and debug directed/random stimulus to ensure design functionality according to specifications.

Skills

Digital Design Verification

SystemVerilog

UVM

Verilog

Functional verification tools

Unix/Linux environment

Tools

VCS

Cadence

Mentor Graphics

Job description

Senior Design Verification Engineer - Data Fabric Systems

As Design Verification Engineer, you will join a leading-edge team responsible for the verification of advanced interconnect systems in state‑of‑the‑art microprocessors. This role focuses on ensuring the functionality, performance, and reliability ofores high‑bandwidth data communication architectures.

We are looking for לחל a team player who is passionate about modern, complex processor architecture, digital design, and verification in general. You should possess strong analytical and problem‑solving skills, excellent communication, a willingness to learn, and readiness to accept challenges.

Responsibilities

• Perform pre‑Silicon Verification of next‑generation high‑performance Microprocessor designs and related IPs.
• Develop, document, and execute verification test plans at the unit level of design hierarchy.
• Develop high‑level language testbench components including stimulus drivers, behavioral models, monitors, and checkers in SystemVerilog.
• Develop, simulate, and debug directed/random stimulus to ensure design functionality according to specifications.

Qualifications

• Minimum of 5 years experience in Digital Design Verification.
• Strong skills with SystemVerilog and UVM; good skills with Verilog.
• Exposure to both maintaining an existing Verification Environment and creating one from scratch.
• Experience with functional verification tools such as VCS, Cadence, and Mentor Graphics.
• Experience working in a Unix/Linux environment.

Seniority level

Mid‑Senior level

Employment type

Full‑time

Industries

ITmaktadırServices and IT Consulting