Senior Functional Verification Engineer — Hybrid

OPENCHIP & SOFTWARE TECHNOLOGIES; Roma; Hybrid; EUR 70,000 - 110,000; Full time

Benefits offered by this job

Hybrid work environment

Remuneration reflecting experience

Growth opportunities

Job summary

Openchip & Software Technologies S.L. in Rome, Italy, seeks a Senior Functional Verification Engineer to lead verification across HW/SW interfaces, using SystemVerilog/UVM, SystemC/C++, and advanced verification techniques.

You will collaborate with architecture, design and software teams to ensure highest performance, with a hybrid work model in Rome and opportunities for mentoring. Strong English and a Master’s degree plus 7+ years in SoC/IP verification are expected.

Qualifications

• Master’s degree in a related engineering field is required.
• 7+ years of experience in verification of complex SoCs or IP.
• Strong knowledge of SystemVerilog/UVM and SystemC/C++.
• Experience with constrained random, functional coverage and design debug.
• Familiarity with Formal Verification and UPF.
• Experience in HW-SW co-verification and simulation.
• Scripting skills (Bash/Perl/Python) are advantageous.
• Good English written and spoken skills.

Responsibilities

• Analyse system and architecture requirements and translate them into verification plans.
• Develop and maintain verification environments in SystemVerilog/UVM/SystemC/C++, including stimuli, checkers, assertions, trackers and coverage.
• Execute verification plans, bring-up DV environments, run regressions and debug failures.
• Leverage simulators, coverage analyzers, UNIX, CI, bug-tracking in the verification process.
• Create and execute test cases to verify functionality in embedded C and SV.
• Identify, isolate and debug issues; drive resolution with design and architecture teams.
• Collaborate with cross-functional teams to achieve verification closure and track coverage.
• Contribute to improvements in verification methodology and organize deliverables.
• Mentor and train junior verification engineers.

Skills

SystemVerilog/UVM

SystemC/C++

Constrained random

Functional coverage

Design debug

Formal verification

UPF

HW-SW co-verification

Bash scripting

Perl scripting

Python scripting

English proficiency

Education

Master Degree in relevant field

Tools

SystemVerilog

UVM

SystemC

C++

Job description

Openchip & Software Technologies S.L. in Rome, Italy, seeks a Senior Functional Verification Engineer to lead verification across HW/SW interfaces, using SystemVerilog/UVM, SystemC/C++, and advanced verification techniques.

You will collaborate with architecture, design and software teams to ensure highest performance, with a hybrid work model in Rome and opportunities for mentoring. Strong English and a Master’s degree plus 7+ years in SoC/IP verification are expected.