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Job summary
A leading IT consulting firm is seeking a Senior Design Verification Engineer to join their team in Rome. In this role, you'll focus on verifying advanced interconnect systems in state-of-the-art microprocessors. The ideal candidate will have at least 5 years of experience in Digital Design Verification, strong skills in SystemVerilog and UVM, and familiarity with functional verification tools. This is a full-time position offering the opportunity to work on cutting-edge technology.
Qualifications
Minimum of 5 years experience in Digital Design Verification.
Strong skills with SystemVerilog and UVM; good skills with Verilog.
Exposure to both maintaining an existing Verification Environment and creating one from scratch.
Experience with functional verification tools such as VCS, Cadence, and Mentor Graphics.
Experience working in a Unix/Linux environment.
Responsibilities
Perform pre-Silicon Verification of next-generation high-performance Microprocessor designs and related IPs.
Develop, document, and execute verification test plans at the unit level of design hierarchy.
Develop high-level language testbench components including stimulus drivers, behavioral models, monitors, and checkers in SystemVerilog.
Develop, simulate, and debug directed/random stimulus to ensure design functionality according to specifications.
Skills
Digital Design Verification
SystemVerilog
UVM
Verilog
Functional verification tools
Unix/Linux environment
Tools
VCS
Cadence
Mentor Graphics
Job description
A leading IT consulting firm is seeking a Senior Design Verification Engineer to join their team in Rome. In this role, you'll focus on verifying advanced interconnect systems in state-of-the-art microprocessors. The ideal candidate will have at least 5 years of experience in Digital Design Verification, strong skills in SystemVerilog and UVM, and familiarity with functional verification tools. This is a full-time position offering the opportunity to work on cutting-edge technology.