Analog Mixed-Signal Verification Engineer

INVENTVM Semiconductor; Pavia; In loco; EUR 50.000 - 70.000; Tempo pieno

Descrizione del lavoro

INVENTVM Semiconductor is seeking an experienced AMS Verification Engineer to join our design team in Italy. You will verify mixed-signal ICs by developing robust verification environments, creating testbenches, and ensuring first-pass silicon success.

You will collaborate with analog and digital designers throughout the product development cycle, develop models using Verilog-A/Verilog-AMS, and drive simulations including Monte Carlo and regression tests to validate functionality.

Competenze

• Master's degree in Electrical Engineering, Electronics Engineering or related field.
• Solid understanding of analog and mixed-signal circuit fundamentals.
• Experience with AMS simulation and verification tools (Cadence Virtuoso, Spectre, Xcelium).
• Knowledge of Verilog-AMS, Verilog-A, SystemVerilog, or RNM.
• Familiarity with scripting languages such as Python, Tcl, Perl, or Shell.
• Strong debugging and problem-solving skills.
• Good communication and teamwork abilities.

Mansioni

• Develop and execute verification plans for analog and mixed-signal IPs and SoCs.
• Create, maintain, and enhance AMS verification environments using industry-standard methodologies.
• Develop behavioral models of analog blocks using Verilog-A, Verilog-AMS, SystemVerilog RNM, or equivalent modeling languages.
• Design testbenches, stimuli, checkers, assertions, and coverage metrics to validate mixed-signal functionality.
• Perform functional, corner, Monte Carlo, and regression simulations.
• Collaborate with analog and digital design teams to identify, debug, and resolve functional issues.
• Support integration and verification of analog IPs within larger digital or mixed-signal SoCs.
• Analyze simulation results and communicate findings through clear technical reports.
• Contribute to verification methodology improvements, automation, and scripting.
• Support silicon bring-up and correlation between simulation and laboratory measurements when required.

Conoscenze

Verilog-AMS

Verilog-A

SystemVerilog

RNM (Real Number Modeling)

Python

Tcl

Perl

Shell

Formazione

Master's degree in Electrical Engineering

Strumenti

Cadence Virtuoso

Spectre

Xcelium

Descrizione del lavoro

INVENTVM is actively looking for a talented AMS Verification Engineer to join the design team.

In this role, you will be responsible for verifying mixed-signal and analog/mixed-signal (AMS) integrated circuits by developing robust verification environments, creating testbenches, and ensuring first-pass silicon success. You will work closely with analog and digital designers throughout the product development cycle.

Key Responsibilities

• Develop and execute verification plans for analog and mixed-signal IPs and SoCs
• Create, maintain, and enhance AMS verification environments using industry-standard methodologies
• Develop behavioral models of analog blocks using Verilog-A, Verilog-AMS, SystemVerilog RNM, or equivalent modeling languages
• Design testbenches, stimuli, checkers, assertions, and coverage metrics to validate mixed-signal functionality
• Perform functional, corner, Monte Carlo, and regression simulations
• Collaborate with analog and digital design teams to identify, debug, and resolve functional issues
• Support integration and verification of analog IPs within larger digital or mixed-signal SoCs
• Analyze simulation results and communicate findings through clear technical reports
• Contribute to verification methodology improvements, automation, and scripting
• Support silicon bring-up and correlation between simulation and laboratory measurements when required

Required Qualifications

• Master's degree in Electrical Engineering, Electronics Engineering, or a related field
• Solid understanding of analog and mixed-signal circuit fundamentals, including:
  • >> Operational amplifiers
  • >> Comparators
  • >> ADCs and DACs
  • >> PLLs (preferred)
  • >> Voltage regulators and references
  • >> Switched-capacitor circuits
• Experience with AMS simulation and verification tools (e.g., Cadence Virtuoso, Spectre, Xcelium)
• Knowledge of Verilog-AMS, Verilog-A, SystemVerilog, or Real Number Modeling (RNM)
• Familiarity with scripting languages such as Python, Tcl, Perl, or Shell
• Strong debugging and problem-solving skills
• Good communication skills and ability to work effectively in cross-functional teams

Desirable Qualifications

• Experience with UVM-based verification environments.
• Knowledge of digital verification methodologies.
• Familiarity with mixed-signal modeling techniques and abstraction levels.
• Experience with low-power verification concepts.
• Understanding of CMOS device operation and semiconductor fundamentals.

All INVENTVM positions offer a stake in the company equity that also entitles to receive dividends, competitive benefits, sustainable work logistics aimed at balancing personal life and project deadlines.