Senior Engineer Functional Verification

OPENCHIP & SOFTWARE TECHNOLOGIES; Roma; Hybrid; EUR 70,000 - 110,000; Full time

Benefits offered by this job

Hybrid work environment

Remuneration reflecting experience

Growth opportunities

Job summary

Openchip & Software Technologies S.L. in Rome, Italy, seeks a Senior Functional Verification Engineer to lead verification across HW/SW interfaces, using SystemVerilog/UVM, SystemC/C++, and advanced verification techniques.

You will collaborate with architecture, design and software teams to ensure highest performance, with a hybrid work model in Rome and opportunities for mentoring. Strong English and a Master’s degree plus 7+ years in SoC/IP verification are expected.

Qualifications

• Master’s degree in a related engineering field is required.
• 7+ years of experience in verification of complex SoCs or IP.
• Strong knowledge of SystemVerilog/UVM and SystemC/C++.
• Experience with constrained random, functional coverage and design debug.
• Familiarity with Formal Verification and UPF.
• Experience in HW-SW co-verification and simulation.
• Scripting skills (Bash/Perl/Python) are advantageous.
• Good English written and spoken skills.

Responsibilities

• Analyse system and architecture requirements and translate them into verification plans.
• Develop and maintain verification environments in SystemVerilog/UVM/SystemC/C++, including stimuli, checkers, assertions, trackers and coverage.
• Execute verification plans, bring-up DV environments, run regressions and debug failures.
• Leverage simulators, coverage analyzers, UNIX, CI, bug-tracking in the verification process.
• Create and execute test cases to verify functionality in embedded C and SV.
• Identify, isolate and debug issues; drive resolution with design and architecture teams.
• Collaborate with cross-functional teams to achieve verification closure and track coverage.
• Contribute to improvements in verification methodology and organize deliverables.
• Mentor and train junior verification engineers.

Skills

SystemVerilog/UVM

SystemC/C++

Constrained random

Functional coverage

Design debug

Formal verification

UPF

HW-SW co-verification

Bash scripting

Perl scripting

Python scripting

English proficiency

Education

Master Degree in relevant field

Tools

SystemVerilog

UVM

SystemC

C++

Job description

The Role

As a Senior Functional Verification Engineer, you will be interfacing with architecture, design, physical implementation and software teams in order to make sure that the systems are performing to the highest level. Your work may involve high-level modelling, UVM, HW/SW Co-Debug, Simulation Acceleration support.

Key Responsibilities

• Reading and analysing the system requirements and architecture requirement documents.
• Developing Verification environment development and maintenance in SystemVerilog/UVM/SystemC/C++, including all the respective components such as Stimulus, Checkers, Assertions, Trackers, and Coverage.
• Executing Verification Plans, including Design Bring-up, DV environment Bring-up, Regressions and Debug of the test failures.
• Using the standard tools and flows of the verification process (Simulators, Coverage Analyzers, Unix, Continuous Integration, Bug Tracking, …).
• Create and execute testcases to verify the functionality, performance, and robustness in embedded C and SV.
• Identify, isolate, and debug issues found during verification, leveraging simulation and debugging tools to root-cause failures and drive resolution with design and architecture teams.
• Work closely with cross-functional teams to achieve verification closure, conducting coverage analysis, bug tracking, and regression testing to ensure the quality and completeness of verification activities.
• Participation to verification methodology improvements.
• Organize work and deliverables between skills, internal and external teams.
• Opportunities for mentoring and training the next generation of verification engineers.

Qualifications

• Master Degree in relevant field.
• Min 7 years of experience in relevant field of Verification of complex SoC or IP.
• Experience in
• SystemVerilog/UVM
• SystemC/C++
• Experience in Constrained random, Functional Coverage development, design debug.
• Experience in Formal Verification, UPF.
• Experience in HW-SW co-verification and simulation.
• Some previous experience in Firmware based verification is a good to have.
• Some knowledge of scripting languages like Bash/Perl/Python.
• Use of verification management tools.
• Strong debugging and problem-solving skills, with the ability to effectively analyze and resolve complex verification issues.
• Good level of English, both written and spoken is mandatory.

Experience In The Following Are a Plus

• Experience in Firmware-based verification.
• Knowledge in metrics-driven verification.
• Insights of NOC and other IPs or standard peripherals like PCIe, DDR, HBM …

Soft Kills

• Team player, able to work with multiple cultures both on site and remotely.
• Autonomous and flexible

What do we offer?

• Join an innovative team and experience company growth.
• We believe in investing in our employees and providing them with the opportunities they need to grow and develop their careers.
• Enjoy a hybrid work environment.
• We also offer flexible schedule.
• We offer a remuneration that values your experience.
• Working place: Rome (Italy)

We are looking for outstanding people willing to join our mission to change this industry and help to build a better world.

At Openchip & Software Technologies S.L., we believe a diverse and inclusive team is the key to groundbreaking ideas. We foster a work environment where everyone feels valued, respected, and empowered to reach their full potential – regardless of race, gender, ethnicity, sexual orientation, or gender identity.