High-Performance CPU RTL & Microarchitecture Engineer

QUALCOMM, Inc.; Piemonte; On-site; EUR 54,000 - 80,000; Full time

Benefits offered by this job

RSU grants

Bonus program

Benefits package

Job summary

Qualcomm Europe, Inc. Italy Branch Office is seeking a CPU RTL Development Engineer to contribute to micro-architecture and RTL ownership, working with chip architects and verification teams to deliver high-performance, power-efficient CPU solutions.

You will engage in performance exploration, RTL refinement, and functional verification to ensure timing and area goals are met across the product lifecycle. A strong background in Verilog/VHDL and ASIC design is required.

Qualifications

• Bachelor's degree in Science, Engineering, or related field.
• 2+ years of ASIC design, verification, validation, integration, or related work experience.
• Master's degree in Science, Engineering, or related field and 1+ year of ASIC experience.
• PhD in Science, Engineering, or related field is also considered.

Responsibilities

• Performance exploration with CPU modelling team.
• Microarchitecture development and specification from early exploration to detailed spec.
• RTL ownership and refinement to meet power, performance, area, timing goals.
• Functional and performance verification support.
• Design delivery with multi-functional teams across timing, area, reliability, testability.

Skills

ASIC design

Microarchitecture

RTL design

Verification

Education

Bachelor's degree in Science/Engineering

Master's degree in Science/Engineering

PhD in Science/Engineering

Tools

Verilog

VHDL

Simulators

Waveform debugging tools

Perl

Python

Job description

Qualcomm Europe, Inc. Italy Branch Office is seeking a CPU RTL Development Engineer to contribute to micro-architecture and RTL ownership, working with chip architects and verification teams to deliver high-performance, power-efficient CPU solutions.

You will engage in performance exploration, RTL refinement, and functional verification to ensure timing and area goals are met across the product lifecycle. A strong background in Verilog/VHDL and ASIC design is required.