CPU Microarchitecture & RTL Design Engineer

QUALCOMM, Inc.

Roma

On-site

EUR 54,000 - 80,000

Full time

3 days ago
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Job summary

Qualcomm Europe, Inc. Italy Branch Office is seeking an engineer in CPU engineering to drive performance exploration, microarchitecture development, RTL ownership, and verification across a full design cycle.

The role involves collaborating with the CPU modeling and verification teams to meet power, timing, and area targets, while delivering robust design implementations and detailed specifications.

Qualifications

  • Bachelor's degree with 2+ years of ASIC design, verification, validation, integration, or related work experience.
  • Master's degree with 1+ year of ASIC design, verification, validation, integration, or related work experience.
  • PhD in Science, Engineering, or related field.

Responsibilities

  • Performance exploration with CPU modeling team.
  • Microarchitecture development and specification from high-level exploration to detailed specs.
  • RTL ownership: development, assessment and refinement to meet power, performance, area and timing goals.
  • Functional verification support for the design verification team.
  • Performance verification support to ensure RTL meets goals.
  • Design delivery with multi-functional teams addressing timing, area, reliability, and testability.

Skills

Microprocessor architecture
Verilog
VHDL
Waveform debugging tools
Logic design principles
Low power microarchitecture
High-performance CPU techniques
Python/Perl scripting

Education

Bachelor's degree in Science, Engineering, or related field
Master's degree in Science, Engineering, or related field
PhD in Science, Engineering, or related field

Tools

Verilog
VHDL

Job description

Qualcomm Europe, Inc. Italy Branch Office is seeking an engineer in CPU engineering to drive performance exploration, microarchitecture development, RTL ownership, and verification across a full design cycle.

The role involves collaborating with the CPU modeling and verification teams to meet power, timing, and area targets, while delivering robust design implementations and detailed specifications.

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