EDA & CAD Flow Engineer for SoC Tapeout

FONDAZIONE CHIPS-IT; Cascina Vignazza; In loco; EUR 60.000 - 90.000; Tempo pieno

Descrizione del lavoro

FONDAZIONE CHIPS-IT seeks a CAD & EDA Flow Engineer to manage and optimize the EDA infrastructure for advanced SoC design up to tape-out.

You will liaise with Cadence, Synopsys and Siemens, install and maintain PDKs across digital, analog and RF workflows, and support foundries for DRC/LVS and tape-out readiness. The role is based in Italy, with options between Pavia and Bologna.

You will also create internal trainings and documentation to accelerate design teams and evolve design flows.

Competenze

• Experience with EDA toolchains and PDKs.
• Experience coordinating with foundries on design rules and tape-out readiness.
• Strong problem-solving, scripting, and automation capabilities.

Mansioni

• Manage EDA tool procurement, licenses, and vendor relationships (Cadence, Synopsys, Siemens).
• Install, configure, and maintain PDKs across digital, analog and RF workflows.
• Act as primary liaison with foundries for PDK installation, DRC/LVS, and issue resolution.
• Maintain and optimize EDA toolchains for synthesis, simulation, verification, and physical implementation; emulation experience is a plus.
• Create and update internal trainings, technical documentation, and best practices for design teams.

Conoscenze

CAD/EDA tools

PDK integration

Vendor management

Strumenti

Cadence

Synopsys

Siemens

Descrizione del lavoro

FONDAZIONE CHIPS-IT seeks a CAD & EDA Flow Engineer to manage and optimize the EDA infrastructure for advanced SoC design up to tape-out.

You will liaise with Cadence, Synopsys and Siemens, install and maintain PDKs across digital, analog and RF workflows, and support foundries for DRC/LVS and tape-out readiness. The role is based in Italy, with options between Pavia and Bologna.

You will also create internal trainings and documentation to accelerate design teams and evolve design flows.