VLSI Design Verification Engineer

HCL Technologies Limited; Bengaluru; On-site; INR 2,000,000 - 4,000,000; Full time

Job summary

HCL Technologies Limited seeks skilled Design Verification (DV) Engineers to validate complex ASIC/SoC/IP designs. You will develop scalable verification environments, create test plans, and ensure functional correctness using advanced methodologies such as UVM.

Collaborate with design and architecture teams to deliver first-time-right silicon. Key responsibilities include developing directed and constrained-random test cases, debugging RTL and gate-level issues, and automating regression flows

Qualifications

• Excellent knowledge of SystemVerilog and UVM.
• Experience with EDA tools such as VCS and Verdi.
• Experience debugging RTL and gate-level simulation issues; PCIe knowledge.

Responsibilities

• Develop directed and constrained-random testcases.
• Debug failures and root-cause issues across RTL, testbench, and tools.
• RTL as well as Gate level simulations.
• Automate regression flows and improve verification productivity.

Skills

SystemVerilog

UVM

RTL debugging

Gate-level simulations

PCIe knowledge

Python scripting

Cross-functional collaboration

Strong analytical

Good communication

Education

B.Tech / M.Tech in Electronics / Electrical / Computer Engineering or equivalent

Tools

VCS

Verdi

Job description

We are Hiring: VLSI Design Verification Engineers.

Experience Level: 4–15 years.

Job Summary:

We are seeking skilled Design Verification (DV) Engineers to validate complex ASIC/SoC/IP designs. The role involves developing scalable verification environments, creating test plans, and ensuring functional correctness through advanced verification methodologies such as UVM.

You will work closely with design, architecture, and physical design teams to deliver first-time-right silicon.

Key Responsibilities:

• Develop directed and constrained-random testcases
• Debug failures and root-cause issues across RTL, testbench, and tools
• RTL as well as Gate level simulations
• Automate regression flows and improve verification productivity

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Required Skills & Qualifications:

Technical Skills:

• Good knowledge of System Verilog.
• Hands-on experience with UVM (Universal Verification Methodology).
• Experience with EDA tools (e.g., VCS, Verdi).
• Experience in debugging RTL and gate level simulation issues.
• Good knowledge of PCIe protocol.

Programming/Scripting.

• Proficiency in Python/Perl/Shell scripting for automation.

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Education

• B.Tech / M.Tech in Electronics / Electrical / Computer Engineering or equivalent

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Soft Skills

• Strong analytical and debugging skills
• Good communication and cross-functional collaboration.