SOC Verification Engineer

UST; Bengaluru; On-site; INR 2,500,000 - 4,000,000; Full time

Job summary

UST Bengaluru is seeking a highly motivated SoC Design Verification Engineer to join our silicon verification team. The role focuses on developing verification strategies for complex ASIC/SoC designs and ensuring functional correctness across the product lifecycle.

You will build SystemVerilog/UVM environments, create tests and coverage models, debug RTL, and automate flows with scripting. Strong knowledge of AXI/AHB/APB and other interfaces is essential.

Qualifications

• Bachelor's or Master's degree in Electronics, Electrical Engineering, Computer Engineering, or related field.
• 4 to 10 years of ASIC/SoC Design Verification experience.
• Strong SystemVerilog and UVM knowledge; testing and coverage experience.
• Proficiency in scripting (Python, Perl, Shell, Tcl).

Responsibilities

• Develop and implement verification plans based on design specifications and architecture requirements.
• Create and maintain SystemVerilog/UVM-based verification environments for IP, subsystem, and SoC-level verification.
• Develop test cases, sequences, scoreboards, checkers, assertions, and coverage models.
• Perform functional verification using simulation, regression, and coverage analysis methodologies.
• Debug RTL and verification environment issues, working closely with design and architecture teams.
• Analyze functional, code, assertion, and toggle coverage metrics and drive closure.
• Support integration and verification of industry-standard protocols such as AXI, AHB, APB, PCIe, USB, Ethernet, UART, SPI, or I2C.
• Participate in design reviews and verification sign-off activities.
• Automate verification flows using scripting languages.

Skills

SystemVerilog

UVM

Test plans

Test cases

Coverage models

Debugging

Bus protocols

Python

Perl

Shell

Tcl

Education

Bachelor's/Master's degree

Tools

VCS

Xcelium

QuestaSim

Riviera

Job description

We are seeking a highly motivated SoC Design Verification Engineer with 4 to 10 years of experience in ASIC/SoC verification. The candidate will be responsible for developing and executing verification strategies for complex SoC designs, ensuring functional correctness and quality throughout the product development lifecycle.

Key Responsibilities:

• Develop and implement verification plans based on design specifications and architecture requirements.
• Create and maintain SystemVerilog/UVM-based verification environments for IP, subsystem, and SoC-level verification.
• Develop test cases, sequences, scoreboards, checkers, assertions, and coverage models.
• Perform functional verification using simulation, regression, and coverage analysis methodologies.
• Debug RTL and verification environment issues, working closely with design and architecture teams.
• Analyze functional, code, assertion, and toggle coverage metrics and drive closure.
• Support integration and verification of industry-standard protocols such as AXI, AHB, APB, PCIe, USB, Ethernet, UART, SPI, or I2C.
• Participate in design reviews and verification sign-off activities.
• Automate verification flows using scripting languages.

Required Qualifications:

• Bachelor's or Master's degree in Electronics, Electrical Engineering, Computer Engineering, or related field.
• 4 to 10 years of experience in ASIC/SoC Design Verification.
• Strong understanding of digital design fundamentals and computer architecture.
• Hands-on experience with SystemVerilog and UVM methodology.
• Experience in writing verification test plans, test cases, assertions, and coverage models.
• Good debugging skills using simulators such as VCS, Xcelium, QuestaSim, or Riviera.
• Knowledge of industry-standard bus protocols such as AXI, AHB, APB, and peripheral interfaces.
• Understanding of coverage-driven verification and constrained random verification methodologies.
• Proficiency in scripting using Python, Perl, Shell, or Tcl.