Design and Verification Engineer

Honeybee Tech Solutions; Bengaluru; On-site; INR 1,200,000 - 2,400,000; Full time

Job summary

Honeybee Tech Solutions in Bengaluru seeks experienced ASIC Design Verification engineers. You will verify IP/Sub-System/SoC, develop UVM environments, and drive verification closure for data center ASICs. Collaboration with cross-functional teams is essential.

Ideal candidates have 5–10 years of ASIC DV experience, strong SystemVerilog/Verilog/UVM skills, and hands-on Python/C/C++ for verification, with Ethernet as a mandatory high-speed protocol.

Qualifications

• 5–10 years of ASIC Design Verification experience.
• Strong hands-on experience in SystemVerilog, Verilog, UVM.
• Experience with AMBA AXI/APB protocols.
• Strong expertise in at least one high-speed protocol: Ethernet (Mandatory), PCIe, RDMA.
• Experience in IP, Cluster, Sub-System, or SoC Verification.
• Hands-on experience with Python/C/C++ for verification.
• Experience in verification planning, testbench development, debugging, functional & code coverage.
• Strong knowledge of networking/data-center ASICs.

Responsibilities

• Develop and execute IP/Sub-System/SoC verification plans.
• Build UVM-based verification environments and functional test cases.
• Perform simulation, formal verification, and emulation for verification closure.
• Debug functional failures and work closely with ASIC Design teams.
• Drive functional and code coverage to achieve verification closure.
• Collaborate with Design, Emulation, Silicon Validation, and Software teams.
• Mentor engineers and contribute to verification methodology improvements.

Skills

SystemVerilog

Verilog

UVM

Python

C++

Networking protocols knowledge

Education

Bachelor's degree in CS/EC/CE or related technical field

Tools

AMBA AXI/APB protocols

Git/SVN/Mercurial

Waveform debugging tools

Automation scripting (Python/Perl/TCL)

Job description

We are hiring experienced ASIC Design Verification (DV) Engineers with expertise in Ethernet and high-speed networking protocols. The role involves IP/Sub-System/SoC verification, UVM-based verification environment development, verification closure, debugging, and collaboration with cross-functional ASIC design teams to deliver first-pass silicon success for data center applications.

Key Responsibilities

• Develop and execute IP/Sub-System/SoC verification plans.
• Build UVM-based verification environments and functional test cases.
• Perform simulation, formal verification, and emulation for verification closure.
• Debug functional failures and work closely with ASIC Design teams.
• Drive functional and code coverage to achieve verification closure.
• Collaborate with Design, Emulation, Silicon Validation, and Software teams.
• Mentor engineers and contribute to verification methodology improvements.

Mandatory Skills

• 5-10 years of ASIC Design Verification experience.
• Strong hands-on experience in SystemVerilog, Verilog, UVM.
• Experience with AMBA AXI/APB protocols.
• Strong expertise in at least one high-speed protocol: Ethernet (Mandatory), PCIe, RDMA.
• Experience in IP, Cluster, Sub-System, or SoC Verification.
• Hands-on experience with Python/C/C++ for verification.
• Experience in verification planning, testbench development, debugging, functional & code coverage.
• Strong knowledge of networking/data-center ASICs.

Preferred Skills

• UVM environment development from scratch.
• Formal Verification, SV Assertions, Emulation.
• Verification of ARM/RISC-V based SoCs.
• High-speed interface verification (Ethernet, PCIe, DDR, HBM).
• Experience with Git/SVN/Mercurial, waveform debugging tools, and automation scripting (Python/Perl/TCL).

Education

• Bachelor's degree in Computer Science, Electronics, Computer Engineering, or a related technical field.

Keywords

ASIC Design Verification, ASIC DV, SystemVerilog, UVM, Verilog, Ethernet, PCIe, RDMA, AXI, APB, SoC Verification, IP Verification, Networking, RTL Verification, Functional Verification, Python, C++, ARM, RISC-V, Emulation, Formal Verification, Data Center ASIC.

Note

Note: Candidates with more than 30 days' notice period will not be considered.