VLSI Design Verification Engineer

HCL Technologies Limited; Chennai; On-site; INR 1,200,000 - 2,400,000; Full time

Job summary

HCL Technologies Limited in India is hiring Design Verification Engineers to validate ASIC/SoC designs. You will develop scalable verification environments, create test plans, and ensure functional correctness using UVM.

You will collaborate with design, architecture, and physical design teams to deliver first-time-right silicon, and handle debugging across RTL, testbench, and tools. Locations include Bengaluru, Noida, Chennai and Hyderabad.

Qualifications

• Proficient in SystemVerilog and UVM.
• Experience with EDA tools like VCS and Verdi.
• Strong debugging of RTL and gate-level simulations.

Responsibilities

• Develop directed and constrained-random testcases.
• Debug failures and root-cause issues across RTL, testbench and tools.
• RTL and Gate level simulations.
• Automate regression flows and improve verification productivity.

Skills

SystemVerilog

UVM

RTL debugging

PCIe protocol

Scripting (Python/Perl/Shell)

Education

B.Tech / M.Tech in ECE / Electronics / Electrical

Tools

VCS

Verdi

Job description

Hi All,

Greetings from HCL Tech.

We are Hiring: VLSI Design Verification Engineers.

Locations: Bengaluru, Noida, Chennai & Hyderabad.

Experience Level: 4-15 years.

Job Summary

We are seeking skilled Design Verification (DV) Engineers to validate complex ASIC/SoC/IP designs. The role involves developing scalable verification environments, creating test plans, and ensuring functional correctness through advanced verification methodologies such as UVM.

You will work closely with design, architecture, and physical design teams to deliver first-time-right silicon.

Key Responsibilities

• Develop directed and constrained-random testcases
• Debug failures and root-cause issues across RTL, testbench, and tools
• RTL as well as Gate level simulations
• Automate regression flows and improve verification productivity

Required Skills & Qualifications

Technical Skills

• Good knowledge of System Verilog.
• Hands-on experience with UVM (Universal Verification Methodology).
• Experience with EDA tools (e.g., VCS, Verdi).
• Experience in debugging RTL and gate level simulation issues.
• Good knowledge of PCIe protocol.

Programming/Scripting

• Proficiency in Python/Perl/Shell scripting for automation.

Education

• B.Tech / M.Tech in Electronics / Electrical / Computer Engineering or equivalent

Soft Skills

• Strong analytical and debugging skills
• Good communication and cross-functional collaboration.