Design and Verification Engineer

Scaledge; Hyderabad, Ahmedabad District, Bengaluru; Hybrid; INR 1,200,000 - 1,600,000; Full time

Job summary

Scaledge is seeking an experienced Design Verification Engineer in Bangalore to join our VLSI/ASIC/SoC verification team. The candidate will design and maintain UVM-based verification environments, develop testbenches, and perform thorough functional verification of IP and SoC blocks.

You will craft verification plans, create constrained-random test cases, and debug issues across simulators such as VCS, Questa, or Xcelium.

Qualifications

• 4+ years of experience in Design Verification.
• Strong knowledge of SystemVerilog.
• Hands-on experience with UVM methodology.
• Experience in testbench development and verification environment setup.
• Good understanding of digital design fundamentals.
• Experience in functional coverage and coverage closure.
• Strong debugging skills using simulation tools.
• Knowledge of PCIe, Ethernet, AMBA AXI/AHB/APB.
• Experience with constrained-random verification.
• Knowledge of assertions and coverage-driven verification.
• Experience with simulators such as VCS, Questa, or Xcelium.

Responsibilities

• Develop and maintain UVM-based verification environments.
• Create verification plans, test plans, and test scenarios based on design specifications.
• Develop SystemVerilog testbenches and verification components.
• Perform functional verification of IP and SoC designs.
• Develop constrained-random and directed test cases.
• Debug simulation failures and identify design issues.
• Perform functional coverage analysis and coverage closure.
• Verify protocols such as PCIe, Ethernet, AMBA AXI/AHB/APB.
• Work closely with RTL design teams to resolve design and verification issues.
• Perform regression testing and ensure verification quality.
• Participate in design reviews and verification planning.
• Develop assertions using SystemVerilog Assertions (SVA).

Skills

SystemVerilog

UVM

IP/SoC verification

Testbench development

Functional coverage

Debugging

PCIe protocol

Ethernet protocol

AMBA protocols

Constrained-random verification

SystemVerilog Assertions

Simulation tools

Tools

VCS

Questa

Xcelium

Job description

Job Description Design Verification Engineer (DV)

Job Title: Design Verification Engineer
Experience: 4+ Years
Location: Bangalore
Domain: VLSI / ASIC / SoC Verification

Job Overview

We are looking for an experienced Design Verification Engineer with strong expertise in SystemVerilog and UVM-based verification methodologies. The candidate should have hands-on experience in IP/SoC verification, testbench development, functional coverage, and debugging. Exposure to protocols such as PCIe, Ethernet, and AMBA will be an added advantage.

Key Responsibilities

• Develop and maintain UVM-based verification environments.
• Create verification plans, test plans, and test scenarios based on design specifications.
• Develop SystemVerilog testbenches and verification components.
• Perform functional verification of IP and SoC designs.
• Develop constrained-random and directed test cases.
• Debug simulation failures and identify design issues.
• Perform functional coverage analysis and coverage closure.
• Verify protocols such as PCIe, Ethernet, AMBA AXI/AHB/APB.
• Work closely with RTL design teams to resolve design and verification issues.
• Perform regression testing and ensure verification quality.
• Participate in design reviews and verification planning.
• Develop assertions using SystemVerilog Assertions (SVA).

Required Skills

• 4+ years of experience in Design Verification.
• Strong knowledge of SystemVerilog.
• Hands-on experience with UVM methodology.
• Experience in testbench development and verification environment setup.
• Good understanding of digital design fundamentals.
• Experience in functional coverage and coverage closure.
• Strong debugging skills using simulation tools.
• Knowledge of protocols such as PCIe, Ethernet, AMBA AXI/AHB/APB.
• Experience with constrained-random verification.
• Knowledge of assertions and coverage-driven verification.
• Experience with simulators such as VCS, Questa, or Xcelium.
• Strong analytical and problem-solving skills.

Preferred Skills

• Hands-on experience in PCIe / Ethernet / AMBA protocol verification.
• Experience in IP-level and SoC-level verification.
• Knowledge of CDC verification.
• Experience with formal verification methodologies.
• Python or scripting knowledge for verification automation.