Senior Design Verification Engineer

MediaTek; Bengaluru; Vor Ort; INR 4.000.000 - 7.000.000; Vollzeit

Zusammenfassung

MediaTek in Bengaluru, India seeks experienced Design Verification professionals to drive verification of complex IPs, subsystems, and SoCs. You will apply SystemVerilog/UVM-based methodologies and deliver high-quality silicon through robust verification environments.

The role demands 8+ years in Design Verification, hands-on SV/UVM expertise, and leadership across projects. You will mentor engineers, collaborate with architecture and software teams, and shape verification plans, coverage, and

Qualifikationen

• 8+ years of hands-on experience in Design Verification.
• Strong expertise in SystemVerilog and UVM.
• Experience verifying IP, Subsystem, and SoC designs.
• Experience with verification planning, coverage-driven verification, and debugging.
• Knowledge of industry-standard verification methodologies.
• Scripting experience with Python, Perl, or Shell is a plus.

Aufgaben

• Lead verification activities for IP, Subsystem, and SoC-level designs.
• Develop and execute comprehensive verification plans.
• Build and enhance UVM/SystemVerilog verification environments.
• Develop testcases, assertions, checkers, and coverage models.
• Drive functional, code, and assertion coverage closure.
• Debug complex design and verification issues.
• Collaborate with architecture, design, validation, and software teams.
• Mentor junior engineers and provide technical leadership.

Kenntnisse

SystemVerilog

UVM

Design Verification

Testbench Development

Python scripting

Tools

Python

Shell

Perl

Jobbeschreibung

We are seeking experienced Design Verification professionals to drive verification of complex IPs, subsystems, and SoCs. The ideal candidate will have strong expertise in SystemVerilog/UVM-based verification methodologies and a proven track record of delivering high-quality silicon.

Key Responsibilities

• Lead verification activities for IP, Subsystem, and SoC-level designs.
• Develop and execute comprehensive verification plans.
• Build and enhance UVM/SystemVerilog verification environments.
• Develop testcases, assertions, checkers, and coverage models.
• Drive functional, code, and assertion coverage closure.
• Debug complex design and verification issues.
• Collaborate closely with architecture, design, validation, and software teams.
• Mentor junior engineers and provide technical leadership across projects.

Required Skills & Experience

• 8+ years of experience in Design Verification.
• Strong hands-on experience in SystemVerilog and UVM.
• Expertise in IP, Subsystem, and/or SoC Verification.
• Experience in verification planning, coverage-driven verification, and debug.
• Strong understanding of industry-standard verification methodologies.
• Experience with scripting languages such as Python, Perl, or Shell is an added advantage.

Preferred Domain Experience

Candidates should have strong experience in one or more of the following areas:

• Ethernet IPs – IP, Subsystem, or SoC Verification
• XPU Chassis – SoC/Subsystem Verification