ASIC Design Lead Level Professional

Tessolve; Coimbatore District, Bengaluru, Hyderabad; Sur place; INR 1 000 000 - 1 500 000; Plein temps

Résumé du poste

Tessolve is looking for an experienced professional in Coimbatore, Tamil Nadu for roles focusing on digital design and implementation. The candidate should have 8-12 years of experience in digital or mixed signal IC design and possess a BS/BEng in Electrical or Electronic engineering, preferably with an MS.

The responsibilities include microarchitecture design, debugging, and providing support for verification to ensure timely closure of design issues. Familiarity with digital design tools like Cadence and Synopsis is required.

Qualifications

• 8-12 years industry experience in digital or mixed signal IC design.
• Knowledge of digital design components such as register file design and state machine architecture.
• Familiarity with TFM tools and flows.

Responsabilités

• Microarchitecture and Module design.
• Develop design constraints and debug functional test issues.
• Support verification efforts for timely design closure.

Connaissances

Verilog coding

Digital design

Low power design

Automation scripting

Verification (System Verilog)

Formation

BS/BEng in Electrical or Electronic engineering

MS in relevant field

Outils

Cadence design tools

Synopsis design tools

Description du poste

Job Responsibilities

• Microarchitecture, Module design and simulation


• Digital design, implementation and integration RTL Coding, Lint, CDC, and Synthesis.


• Develop design constraints and coordinate to debug both functional and DFT test issues.


• Synthesis and P&R constraint generation, including clock tree specification


• Scan insertion and pattern generation


• Support IP/Design Verification/Firmware/Software System to provide the necessary support for timely closure of assigned blocks design and implementation issues.

Job Requirements

• BS/BEng in Electrical or Electronic engineering, MS preferred


• 8-12 years industry experience with BS working in digital or mixed signal IC design


• Digital design knowledge:
  
  
  
  • Verilog coding
  
  
  • Register file design
  
  
  • Serial interfaces
  
  
  • Interconnect fabrics
  
  
  • State machine architecture
  
  
  • Clock domain crossing
  
  
  • Scan and self-test
  
  
  • Synthesis, Linting, STA
  
  
  • Automation scripting and design flows
  
  
  • Verification, including System Verilog knowledge
  
  
  • Low power design, Power intent specification and validation methodology.
  
  
  
  


• System knowledge:
  
  
  
  • Battery management and RISC-V based Subsystems/SOCs.
  
  
  
  


• Knowledge of TFM (Tools, Flows and Methodologies) flows: Simulation, Lint, CDC/RDC and power intent checks UPF.


• Familiarity with Cadence, Synopsis design tools


• Ability to work as part of a team and with low levels of supervision