Sykatiya Technologies - RTL Design Engineer - ASIC/SoC

Sykatiya Technologies Pvt Ltd; Bengaluru; On-site; INR 1,100,000 - 1,700,000; Full time

Job summary

Sykatiya Technologies Pvt Ltd in Bengaluru seeks an experienced EDA engineer to optimize timing, area and power through logic and physical synthesis. You will diagnose timing, area and congestion with RTL and designers, while performing RTL and gate-level power estimation and formal verification.

You will lint RTL, perform DFT analysis, and develop timing constraints for PrimeTime-STA. You will also automate FE-tool workflows and collaborate across Design, DV, Emulation and Physical teams to

Qualifications

• Experience with logic/physical synthesis for timing, area and power optimization.
• Ability to debug timing, area and congestion with RTL and Physical designers.
• Experience in power estimation at RTL and gate level with opportunities for reduction.
• Proficiency in Formal Verification between RTL and gate-level netlists and debugging failures.
• RTL lint and waivers experience with collaboration with design teams.
• DFT analysis experience to improve coverage for stuck-at faults.
• Develop timing constraints for RTL-Synthesis and PrimeTime-STA for blocks and SOC.
• Develop automation scripts for FE-tools including Lint, CDC, RDC, Synthesis, STA, Power.
• Collaborate with Design, DV, Emulation teams; interact with Physical Design for timing/congestion feedback.

Responsibilities

• Run logic/physical Synthesis to optimize timing and area.
• Debug timing/area/congestion with RTL and Physical teams.
• Perform RTL and gate-level power estimation and identify reductions.
• Run Formal Verification between RTL and gate-level netlists and fix issues.
• Carry out RTL lint and create appropriate waivers.
• Perform RTL DFT analysis to improve coverage.
• Develop timing constraints for RTL-Synthesis and PrimeTime-STA.
• Create automation scripts for FE-tools (Lint, CDC, RDC, Synthesis, STA, Power).
• Coordinate with Design, DV, Emulation teams and provide timing/congestion feedback to Physical Design.

Skills

RTL design

Timing closure

Power estimation

Formal verification

RTL lint

DFT analysis

Timing constraints

Automation scripting

Cross-functional collaboration

Tools

PrimeTime-STA

RTL Synthesis

Lint

CDC

RDC

Job description

• Run Logic/Physical Synthesis using advanced optimization techniques and generate optimized Gate Level Netlist for Timing, Area, Power.
• Debug the timing/area/congestion issues and work with RTL & Physical designers to resolve them.
• Perform Power Estimation at RTL and Gate Level and identify power reduction opportunities.
• Run Formal Verification checks between RTL and Gate level netlist and debug the aborts, inconclusive and Logic Equivalency failures.
• Perform RTL Lint and work with the Designers to create waivers.
• Perform RTL DFT Analysis and improve the DFT coverage for Stuck-at faults.
• Develop Timing Constraints for RTL-Synthesis and PrimeTime-STA for the blocks and the top-level including SOC. Analyze the inter-block timing and come up with IO budgets for the various partition blocks.
• Developing Automation scripts and Methodology for all FE-tools including (Lint, CDC, RDC, Synthesis, STA, Power).
• Work closely with the Design Engineers, DV Engineers, Emulation Engineers in supporting them with the handoff tasks. Interact with Physical Design Engineers and provide them with timing/congestion feedback.