RTL Design Lead

Erbity; Bengaluru; On-site; INR 1,800,000 - 2,400,000; Full time

Job summary

Erbity in Bengaluru seeks an experienced RTL Design Engineer to lead RTL development for complex ASIC/SoC projects. You will craft high-quality Verilog/SystemVerilog and define micro-architecture with architecture and verification teams.

You will drive synthesis, lint, CDC, and low-power design methodologies, debug issues across simulation, synthesis, and silicon bring-up, and mentor junior engineers while supporting technical reviews.

Qualifications

• Experience in RTL design for ASIC/SoC projects.
• Hands-on Verilog or SystemVerilog.
• Strong understanding of AMBA protocols (AXI/AHB/APB).
• Experience with synthesis, lint, CDC, and low-power design methodologies.
• Strong debugging and problem-solving skills.
• Prior team handling or technical leadership is preferred.

Responsibilities

• Lead RTL design activities for complex ASIC/SoC development projects.
• Define micro-architecture and implementation strategies with architecture and verification teams.
• Develop high-quality RTL using Verilog/SystemVerilog.
• Drive block-level design, integration, lint, CDC, and synthesis activities.
• Ensure design quality and timely project execution.
• Debug and resolve design issues during simulation, synthesis, and silicon bring-up stages.
• Collaborate with DFT, Physical Design, and Verification teams.
• Mentor junior engineers and support technical reviews.

Skills

RTL Design

Verilog/SystemVerilog

AMBA protocols AXI/AHB/APB

Synthesis/Lint/CDC

Low-power design

Debugging

Leadership

Job description

Job Description:

• Lead RTL design activities for complex ASIC/SoC development projects
• Work closely with architecture and verification teams to define micro-architecture and implementation strategies
• Develop high-quality RTL using Verilog/SystemVerilog
• Drive block-level design, integration, lint, CDC, and synthesis activities
• Ensure design quality and timely project execution
• Debug and resolve design issues during simulation, synthesis, and silicon bring-up stages
• Collaborate with cross-functional teams including DFT, Physical Design, and Verification
• Mentor junior engineers and support technical reviews

Required Skills:

• Strong experience in RTL Design for ASIC/SoC projects
• Hands-on expertise in Verilog/SystemVerilog
• Good understanding of AMBA protocols (AXI/AHB/APB)
• Experience with synthesis, lint, CDC, and low-power design methodologies
• Strong debugging and problem-solving skills
• Prior team handling or technical leadership experience is preferred