RTL Design Lead

Erbity; Ahmedabad District; On-site; INR 1,800,000 - 2,800,000; Full time

Job summary

Erbity in Ahmedabad, India seeks an experienced RTL Design Engineer to lead RTL development for complex ASIC/SoC projects. You will collaborate with architecture and verification teams to define micro-architecture and implement high-quality RTL using Verilog/SystemVerilog.

You will drive block-level design, lint, CDC, and synthesis activities, ensure design quality and timely delivery, debug across simulation and silicon bring-up, and mentor junior engineers while working with DFT, Physical

Qualifications

• Strong experience in RTL Design for ASIC/SoC projects.
• Hands-on expertise in Verilog/SystemVerilog.
• Good understanding of AMBA protocols (AXI/AHB/APB).
• Experience with synthesis, lint, CDC, and low-power design methodologies.
• Strong debugging and problem-solving skills.
• Prior team handling or technical leadership experience is preferred.

Responsibilities

• Lead RTL design activities for complex ASIC/SoC development projects.
• Work with architecture and verification to define micro-architecture and implementation strategies.
• Develop high-quality RTL using Verilog/SystemVerilog.
• Drive block-level design, integration, lint, CDC, and synthesis activities.
• Ensure design quality and timely project execution.
• Debug and resolve design issues during simulation, synthesis, and silicon bring-up stages.
• Collaborate with DFT, Physical Design, and Verification teams.
• Mentor junior engineers and support technical reviews.

Skills

RTL design

Verilog/SystemVerilog

AMBA protocols

Synthesis & lint

Debugging

Leadership

Job description

Job Description:

• Lead RTL design activities for complex ASIC/SoC development projects
• Work closely with architecture and verification teams to define micro-architecture and implementation strategies
• Develop high-quality RTL using Verilog/SystemVerilog
• Drive block-level design, integration, lint, CDC, and synthesis activities
• Ensure design quality and timely project execution
• Debug and resolve design issues during simulation, synthesis, and silicon bring-up stages
• Collaborate with cross-functional teams including DFT, Physical Design, and Verification
• Mentor junior engineers and support technical reviews

Required Skills:

• Strong experience in RTL Design for ASIC/SoC projects
• Hands-on expertise in Verilog/SystemVerilog
• Good understanding of AMBA protocols (AXI/AHB/APB)
• Experience with synthesis, lint, CDC, and low-power design methodologies
• Strong debugging and problem-solving skills
• Prior team handling or technical leadership experience is preferred