RTL Engineers (STA/Synthesis) -- Bangalore

Maxvytech; Bengaluru; On-site; INR 1,200,000 - 1,800,000; Full time

Job summary

A leading tech firm in Bengaluru is seeking RTL Engineers with expertise in STA/Synthesis. The role involves ownership of synthesis constraints and ECO flows, requiring 5 years of experience and strong scripting skills. Candidates should have worked on timing closures and be familiar with high-speed interfaces. Competitive compensation and opportunities for professional growth are offered.

Qualifications

• 5 years of experience in RTL design with emphasis on STA/Synthesis.
• Strong scripting skills with Perl, TCL, C-shell.
• Experience with high-speed interfaces like DDR, RGMII.

Responsibilities

• Handson ownership of Synthesis / Constraints / STA / ECO flow.
• Participate in design reviews and design closure discussions.
• Develop or enhance scripts for various design closure activities.

Skills

Synthesis

STA

Scripting

Timing Closure

ECO implementation

Education

B.E, M.E, M.Tech, B.Tech

Tools

DC

Primetime

Job description

RTL Engineers (STA/Synthesis)

Location : Bangalore

Experience : 5 Years

Education : B.E, M.E, M.Tech, B.Tech

Role :

RTL engineers having experience on STA/Synthesis

Job Description :

• Handson ownership of Synthesis / Constraints / STA / ECO flow.
• Expert in running Block level and Chip level STA in MCMM, DMSA environments.
• Must have worked on multiple timing closure and constraint development for high-speed interfaces like DDR, RGMII, SD, USB, SPI, NAND etc.
• Must have worked on ECO implementation cycles – functional, timing interacting with RTL/PD/DFT teams to resolve all implementation issues.
• Participate in design reviews and design closure discussions.
• Develop or enhance scripts for various design closure activities.
• Good understanding of complete physical design flow.
• Must have gone through multiple tapeout cycles, revisions and ECOs.
• Expertise with Synthesis, STA tools (like DC, Primetime) is a must.
• Strong scripting skills using Perl, TCL, C-shell, Make and/or other scripting languages.
• Timing characterization and post silicon timing correlation experience a plus.
• Experience/project work on critical path simulation, clock path simulation (jitter/duty cycle) with Spice a plus.
• Experience with CDC, Constraint verification, lint checks is a plus.