Rtl Design Engineer

Sykatiya Technologies; Bengaluru; On-site; INR 1,800,000 - 3,000,000; Full time

Job summary

Sykatiya Technologies in Bengaluru is seeking a skilled RTL Design Engineer to drive RTL coding, CDC, lint, and regression checks in a collaborative environment with Design, DV, and Emulation teams. You will interact with Physical Design engineers to provide timing and congestion feedback and contribute to power optimization efforts.

The role requires strong hands-on experience in RTL design, formal verification, DFT, and timing closure, with emphasis on delivering reliable gate-level netlists

Qualifications

• Experience in RTL design and verification workflows.
• Knowledge of timing, area and power constraints.
• Experience with DFT and stuck-at testing.

Responsibilities

• Run Logic/Physical Synthesis using advanced optimization techniques and generate optimized Gate Level Netlist for timing, area, and power.
• Debug timing, area and congestion issues and collaborate with RTL and Physical designers to resolve them.
• Perform Power Estimation at RTL and Gate Level and identify power reduction opportunities.
• Run Formal Verification checks between RTL and Gate-level netlists and debug aborts, inconclusive results and logic equivalency failures.
• Perform RTL Lint and collaborate with Designers to create waivers.
• Perform RTL DFT Analysis and improve DFT coverage for stuck-at faults.
• Develop Timing Constraints for RTL-Synthesis and PrimeTime-STA for blocks and toplevel including SOC.
• Develop automation scripts and methodologies for FE-tools including Lint, CDC, RDC, Synthesis, STA, Power.

Skills

RTL Coding

CDC

Lint

Regression checks

Timing constraints

Power estimation

Formal verification

DFT analysis

SOC timing/IO budgets

Tools

PrimeTime-STA

Job description

Role & responsibilities

We are seeking a highly skilled RTL Design Engineer with strong expertise in RTL Coding, CDC, Lint and

Regression checks.

In this role, you will work closely the Design Engineers, DV Engineers, Emulation Engineers in

supporting them with the handoff tasks. Interact with Physical Design Engineers and provide

them with timing/congestion feedback.

Responsibilities

• Run Logic/Physical Synthesis using advanced optimization techniques and generate optimized

Gate Level Netlist for Timing, Area, Power.

• Debug the timing/area/congestion issues and work with RTL & Physical designers to resolve

them.

• Perform Power Estimation at RTL and Gate Level and identify power reduction opportunities.
• Run Formal Verification checks between RTL and Gate level netlist and debug the aborts,

inconclusive and Logic Equivalency failures.

• Perform RTL Lint and work with the Designers to create waivers.
• Perform RTL DFT Analysis and improve the DFT coverage for Stuck-at faults.
• Develop Timing Constraints for RTL-Synthesis and PrimeTime-STA for the blocks and the toplevel including SOC. Analyze the inter-block timing and come up with IO budgets for the various

partition blocks.

• Developing Automation scripts and Methodology for all FE-tools including (Lint, CDC, RDC,

Synthesis, STA, Power)

Preferred candidate profile