ASIC RTL Design Lead

Mulya Technologies; Ernakulam; On-site; INR 2,800,000 - 5,000,000; Full time

Job summary

Among is seeking a Senior ASIC Engineer to drive IP RTL design and SOC integration. The role emphasizes RTL quality checks, linting, and CDC verification, with a focus on AMBA protocols and timing concepts. Experience with Spyglass Lint/CDC and Synopsys DC is preferred.

You will collaborate with PD, VERIF, and SW teams to resolve cross-subsystem design queries and reviews. Strong Verilog/SystemVerilog expertise, plus scripting skills (Make, Perl, shell, Python) and ARM debug knowledge are highly

Qualifications

• Expertise in IP design, Subsystem/Cluster and SoC level integration using Verilog/System Verilog.
• In depth knowledge on RTL quality checks (Lint, CDC).
• Knowledge of synthesis and low power is a plus.
• Good understanding of AMBA bus protocols (AXI, AHB, ATB, APB).
• Good understanding of timing concepts.
• Understanding of scripting languages like Make flow, Perl, shell, python etc.
• Understanding of processor architecture and/or ARM debug architecture is a plus.
• Able to help and debug issues for multiple subsystems.
• Able to create/review design documents for multiple subsystems.
• Able to support physical design, verification, DFT and SW teams on design queries and reviews.

Responsibilities

• Lead IP RTL design targeted for SOC and integration tasks.
• Perform RTL quality checks and linting on design blocks.
• Coordinate with PD, VERIF and SW teams for design reviews.
• Assist in timing closure and low-power considerations.
• Work with AMBA protocol implementations and related interfaces.
• Prepare design documents and technical reviews for multiple subsystems.

Skills

RTL Design

RTL Coding

RTL Quality Checks

IP Design

SOC Integration

Scripting - Make

Scripting - Perl

Scripting - Shell

Scripting - Python

ARM Debug

Processor Architecture

AMBA Protocols

Timing Concepts

Tools

Spyglass Lint/CDC

Synopsys DC

Job description

Among. The top 4 IT companies, in India ranked by market capitalization and revenue

Experience-11+ years

Mandatory Skill : (RTL Design, RTL Coding & Integration, RTL quality checks (Lint, CDC), IP, targeted for SOC, Static checks, Protocols - PCIe, DDR, Ethernet,I2C, UART, SPI)

Senior ASIC Engineer (IP RTL design targeted for SOC, Static checks, some basic protocols)

Expertise in IP design, Subsystem/Cluster and SoC level integration using Verilog/System Verilog

In depth knowledge on RTL quality checks (Lint, CDC)

Knowledge of synthesis and low power is a plus

Good understanding of AMBA bus protocols (AXI, AHB, ATB, APB)

Good understanding of timing concepts

Knowledge of one or more of the interface protocols

• b. DDR
• c. Ethernet
• d. I2C, UART, SPI

Expertise in setting up and using tools like

• a. Spyglass Lint/CDC
• b. Synopsys DC

Understanding of scripting languages like Make flow, Perl ,shell, python etc

Understanding of processor architecture and/or ARM debug architecture is a plus

Able to help and debug issues for multiple subsystems

Able to create/review design documents for multiple subsystems

Able to support physical design, verification, DFT and SW teams on design queries and reviews