RTL Design Lead

Erbity; Dadri; On-site; INR 800,000 - 1,200,000; Full time

Job summary

Erbity is looking for a skilled RTL Design Engineer in Dadri, India. The role involves leading RTL design for complex ASIC/SoC projects and collaborating closely with architecture and verification teams. Candidates should have strong experience in Verilog/SystemVerilog and a solid understanding of AMBA protocols.

This position provides an opportunity to mentor junior engineers and ensure design quality. If you have strong debugging skills and prior team handling experience, we encourage you to apply.

Qualifications

• Strong experience in RTL Design for ASIC/SoC projects.
• Hands-on expertise in Verilog/SystemVerilog.
• Good understanding of AMBA protocols (AXI/AHB/APB).
• Experience with synthesis, lint, CDC, and low-power design methodologies.
• Strong debugging and problem-solving skills.
• Prior team handling or technical leadership experience is preferred.

Responsibilities

• Lead RTL design activities for complex ASIC/SoC development projects.
• Work closely with architecture and verification teams to define micro-architecture.
• Develop high-quality RTL using Verilog/SystemVerilog.
• Drive block-level design, integration, lint, CDC, and synthesis activities.
• Ensure design quality and timely project execution.
• Debug design issues during simulation, synthesis, and silicon bring-up.
• Collaborate with cross-functional teams including DFT and Verification.
• Mentor junior engineers and support technical reviews.

Tools

Verilog/SystemVerilog

Synthesis tools

Lint tools

CDC design methodologies

Job description

Job Description

• Lead RTL design activities for complex ASIC/SoC development projects
• Work closely with architecture and verification teams to define micro‑architecture and implementation strategies
• Develop high‑quality RTL using Verilog/SystemVerilog
• Drive block‑level design, integration, lint, CDC, and synthesis activities
• Ensure design quality and timely project execution
• Debug and resolve design issues during simulation, synthesis, and silicon bring‑up stages
• Collaborate with cross‑functional teams including DFT, Physical Design, and Verification
• Mentor junior engineers and support technical reviews

Required Skills

• Strong experience in RTL Design for ASIC/SoC projects
• Hands‑on expertise in Verilog/SystemVerilog
• Good understanding of AMBA protocols (AXI/AHB/APB)
• Experience with synthesis, lint, CDC, and low‑power design methodologies
• Strong debugging and problem‑solving skills
• Prior team handling or technical leadership experience is preferred